i2c: imx: add INT flag and IEN bit operatation codes
This add bits operation macro that differ between SoCs. Interrupt flags clear operation in I2SR differ between SoCs: write zero to clear(w0c) INT flag on i.MX, but write one to clear(w1c) INT flag on Vybrid. I2C module enable operation in I2CR also differ between SoCs: set I2CR_IEN bit enable the module on i.MX, but clear I2CR_IEN bit enable the module on Vybrid. Signed-off-by: Jingchang Lu <b35083@freescale.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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@ -95,6 +95,22 @@
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#define I2CR_IIEN 0x40
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#define I2CR_IIEN 0x40
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#define I2CR_IEN 0x80
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#define I2CR_IEN 0x80
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/* register bits different operating codes definition:
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* 1) I2SR: Interrupt flags clear operation differ between SoCs:
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* - write zero to clear(w0c) INT flag on i.MX,
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* - but write one to clear(w1c) INT flag on Vybrid.
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* 2) I2CR: I2C module enable operation also differ between SoCs:
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* - set I2CR_IEN bit enable the module on i.MX,
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* - but clear I2CR_IEN bit enable the module on Vybrid.
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*/
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#define I2SR_CLR_OPCODE_W0C 0x0
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#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
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#define I2CR_IEN_OPCODE_0 0x0
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#define I2CR_IEN_OPCODE_1 I2CR_IEN
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#define IMX_I2SR_CLR_OPCODE I2SR_CLR_OPCODE_W0C
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#define IMX_I2CR_IEN_OPCODE I2CR_IEN_OPCODE_1
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/** Variables ******************************************************************
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/** Variables ******************************************************************
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*******************************************************************************/
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*******************************************************************************/
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@ -242,8 +258,8 @@ static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
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clk_prepare_enable(i2c_imx->clk);
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clk_prepare_enable(i2c_imx->clk);
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imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
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imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
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/* Enable I2C controller */
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/* Enable I2C controller */
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imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
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imx_i2c_write_reg(IMX_I2SR_CLR_OPCODE, i2c_imx, IMX_I2C_I2SR);
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imx_i2c_write_reg(I2CR_IEN, i2c_imx, IMX_I2C_I2CR);
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imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE, i2c_imx, IMX_I2C_I2CR);
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/* Wait controller to be stable */
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/* Wait controller to be stable */
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udelay(50);
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udelay(50);
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@ -287,7 +303,7 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
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}
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}
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/* Disable I2C controller */
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/* Disable I2C controller */
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imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
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imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE ^ I2CR_IEN, i2c_imx, IMX_I2C_I2CR);
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clk_disable_unprepare(i2c_imx->clk);
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clk_disable_unprepare(i2c_imx->clk);
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}
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}
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@ -339,6 +355,7 @@ static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
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/* save status register */
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/* save status register */
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i2c_imx->i2csr = temp;
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i2c_imx->i2csr = temp;
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temp &= ~I2SR_IIF;
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temp &= ~I2SR_IIF;
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temp |= (IMX_I2SR_CLR_OPCODE & I2SR_IIF);
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
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wake_up(&i2c_imx->queue);
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wake_up(&i2c_imx->queue);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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@ -596,8 +613,8 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
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i2c_imx_set_clk(i2c_imx, bitrate);
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i2c_imx_set_clk(i2c_imx, bitrate);
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/* Set up chip registers to defaults */
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/* Set up chip registers to defaults */
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imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
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imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE ^ I2CR_IEN, i2c_imx, IMX_I2C_I2CR);
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imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
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imx_i2c_write_reg(IMX_I2SR_CLR_OPCODE, i2c_imx, IMX_I2C_I2SR);
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/* Add I2C adapter */
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/* Add I2C adapter */
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ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
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ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
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