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MIPS: features: Add initial support for TLBINVF capable cores 

New Aptiv cores support the TLBINVF instruction for flushing
the VTLB.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6130/
hifive-unleashed-5.1
Leonid Yegoshin 2013-11-14 16:12:23 +00:00 committed by Ralf Baechle
parent c01905eeee
commit 1745c1ef88
3 changed files with 9 additions and 0 deletions
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3
arch/mips/include/asm/cpu-features.h
View File

@ -20,6 +20,9 @@
#ifndef cpu_has_tlb
#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
#endif
#ifndef cpu_has_tlbinv
#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
#endif
/*
* For the moment we don't consider R6000 and R8000 so we can assume that

1
arch/mips/include/asm/cpu.h
View File

@ -351,6 +351,7 @@ enum cpu_type_enum {
#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */
/*
* CPU ASE encodings

5
arch/mips/kernel/cpu-probe.c
View File

@ -286,6 +286,11 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c)
&& cpu_has_tlb)
c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
if (cpu_has_tlb) {
if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
c->options |= MIPS_CPU_TLBINV;
}
c->kscratch_mask = (config4 >> 16) & 0xff;
return config4 & MIPS_CONF_M;