MIPS: ath25: add interrupts handling routines
Add interrupts initialization and handling routines, also add AHB bus error interrupt handlers for both SoCs families. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8240/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Sergey Ryazanov
Ralf Baechle
parent
ba91034503
commit
1753e74ed8
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@ -103,6 +103,7 @@ config ATH25
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select CSRC_R4K
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select DMA_NONCOHERENT
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select IRQ_CPU
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select IRQ_DOMAIN
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_32BIT_KERNEL
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@ -16,6 +16,9 @@
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/reboot.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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@ -26,6 +29,7 @@
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#include "ar2315_regs.h"
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static void __iomem *ar2315_rst_base;
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static struct irq_domain *ar2315_misc_irq_domain;
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static inline u32 ar2315_rst_reg_read(u32 reg)
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{
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@ -46,6 +50,116 @@ static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
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ar2315_rst_reg_write(reg, ret);
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}
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static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
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{
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ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
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ar2315_rst_reg_read(AR2315_AHB_ERR1);
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pr_emerg("AHB fatal error\n");
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machine_restart("AHB error"); /* Catastrophic failure */
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return IRQ_HANDLED;
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}
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static struct irqaction ar2315_ahb_err_interrupt = {
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.handler = ar2315_ahb_err_handler,
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.name = "ar2315-ahb-error",
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};
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static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
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ar2315_rst_reg_read(AR2315_IMR);
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unsigned nr, misc_irq = 0;
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if (pending) {
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struct irq_domain *domain = irq_get_handler_data(irq);
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nr = __ffs(pending);
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misc_irq = irq_find_mapping(domain, nr);
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}
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if (misc_irq) {
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if (nr == AR2315_MISC_IRQ_GPIO)
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ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
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else if (nr == AR2315_MISC_IRQ_WATCHDOG)
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ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
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generic_handle_irq(misc_irq);
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} else {
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spurious_interrupt();
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}
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}
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static void ar2315_misc_irq_unmask(struct irq_data *d)
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{
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ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
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}
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static void ar2315_misc_irq_mask(struct irq_data *d)
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{
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ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
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}
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static struct irq_chip ar2315_misc_irq_chip = {
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.name = "ar2315-misc",
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.irq_unmask = ar2315_misc_irq_unmask,
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.irq_mask = ar2315_misc_irq_mask,
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};
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static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
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return 0;
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}
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static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
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.map = ar2315_misc_irq_map,
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};
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/*
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* Called when an interrupt is received, this function
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* determines exactly which interrupt it was, and it
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* invokes the appropriate handler.
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*
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* Implicitly, we also define interrupt priority by
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* choosing which to dispatch first.
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*/
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static void ar2315_irq_dispatch(void)
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{
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u32 pending = read_c0_status() & read_c0_cause();
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if (pending & CAUSEF_IP3)
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do_IRQ(AR2315_IRQ_WLAN0);
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else if (pending & CAUSEF_IP2)
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do_IRQ(AR2315_IRQ_MISC);
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else if (pending & CAUSEF_IP7)
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do_IRQ(ATH25_IRQ_CPU_CLOCK);
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else
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spurious_interrupt();
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}
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void __init ar2315_arch_init_irq(void)
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{
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struct irq_domain *domain;
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unsigned irq;
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ath25_irq_dispatch = ar2315_irq_dispatch;
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domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
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&ar2315_misc_irq_domain_ops, NULL);
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if (!domain)
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panic("Failed to add IRQ domain");
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irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
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setup_irq(irq, &ar2315_ahb_err_interrupt);
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irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
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irq_set_handler_data(AR2315_IRQ_MISC, domain);
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ar2315_misc_irq_domain = domain;
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}
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static void ar2315_restart(char *command)
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{
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void (*mips_reset_vec)(void) = (void *)0xbfc00000;
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@ -3,11 +3,13 @@
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#ifdef CONFIG_SOC_AR2315
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void ar2315_arch_init_irq(void);
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void ar2315_plat_time_init(void);
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void ar2315_plat_mem_setup(void);
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#else
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static inline void ar2315_arch_init_irq(void) {}
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static inline void ar2315_plat_time_init(void) {}
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static inline void ar2315_plat_mem_setup(void) {}
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@ -14,6 +14,29 @@
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#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
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#define __ASM_MACH_ATH25_AR2315_REGS_H
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/*
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* IRQs
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*/
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#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
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#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
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#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
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#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
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#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
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/*
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* Miscellaneous interrupts, which share IP2.
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*/
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#define AR2315_MISC_IRQ_UART0 0
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#define AR2315_MISC_IRQ_I2C_RSVD 1
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#define AR2315_MISC_IRQ_SPI 2
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#define AR2315_MISC_IRQ_AHB 3
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#define AR2315_MISC_IRQ_APB 4
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#define AR2315_MISC_IRQ_TIMER 5
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#define AR2315_MISC_IRQ_GPIO 6
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#define AR2315_MISC_IRQ_WATCHDOG 7
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#define AR2315_MISC_IRQ_IR_RSVD 8
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#define AR2315_MISC_IRQ_COUNT 9
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/*
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* Address map
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*/
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@ -16,6 +16,9 @@
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/reboot.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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@ -26,6 +29,7 @@
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#include "ar5312_regs.h"
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static void __iomem *ar5312_rst_base;
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static struct irq_domain *ar5312_misc_irq_domain;
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static inline u32 ar5312_rst_reg_read(u32 reg)
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{
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@ -46,6 +50,114 @@ static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
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ar5312_rst_reg_write(reg, ret);
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}
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static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
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{
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u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
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u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
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u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
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u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
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pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
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proc_addr, proc1, dma_addr, dma1);
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machine_restart("AHB error"); /* Catastrophic failure */
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return IRQ_HANDLED;
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}
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static struct irqaction ar5312_ahb_err_interrupt = {
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.handler = ar5312_ahb_err_handler,
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.name = "ar5312-ahb-error",
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};
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static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
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ar5312_rst_reg_read(AR5312_IMR);
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unsigned nr, misc_irq = 0;
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if (pending) {
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struct irq_domain *domain = irq_get_handler_data(irq);
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nr = __ffs(pending);
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misc_irq = irq_find_mapping(domain, nr);
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}
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if (misc_irq) {
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generic_handle_irq(misc_irq);
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if (nr == AR5312_MISC_IRQ_TIMER)
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ar5312_rst_reg_read(AR5312_TIMER);
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} else {
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spurious_interrupt();
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}
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}
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/* Enable the specified AR5312_MISC_IRQ interrupt */
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static void ar5312_misc_irq_unmask(struct irq_data *d)
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{
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ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
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}
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/* Disable the specified AR5312_MISC_IRQ interrupt */
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static void ar5312_misc_irq_mask(struct irq_data *d)
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{
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ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
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ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
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}
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static struct irq_chip ar5312_misc_irq_chip = {
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.name = "ar5312-misc",
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.irq_unmask = ar5312_misc_irq_unmask,
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.irq_mask = ar5312_misc_irq_mask,
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};
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static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
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return 0;
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}
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static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
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.map = ar5312_misc_irq_map,
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};
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static void ar5312_irq_dispatch(void)
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{
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u32 pending = read_c0_status() & read_c0_cause();
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if (pending & CAUSEF_IP2)
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do_IRQ(AR5312_IRQ_WLAN0);
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else if (pending & CAUSEF_IP5)
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do_IRQ(AR5312_IRQ_WLAN1);
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else if (pending & CAUSEF_IP6)
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do_IRQ(AR5312_IRQ_MISC);
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else if (pending & CAUSEF_IP7)
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do_IRQ(ATH25_IRQ_CPU_CLOCK);
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else
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spurious_interrupt();
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}
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void __init ar5312_arch_init_irq(void)
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{
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struct irq_domain *domain;
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unsigned irq;
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ath25_irq_dispatch = ar5312_irq_dispatch;
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domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
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&ar5312_misc_irq_domain_ops, NULL);
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if (!domain)
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panic("Failed to add IRQ domain");
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irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
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setup_irq(irq, &ar5312_ahb_err_interrupt);
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irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
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irq_set_handler_data(AR5312_IRQ_MISC, domain);
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ar5312_misc_irq_domain = domain;
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}
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static void ar5312_restart(char *command)
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{
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/* reset the system */
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@ -3,11 +3,13 @@
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#ifdef CONFIG_SOC_AR5312
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void ar5312_arch_init_irq(void);
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void ar5312_plat_time_init(void);
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void ar5312_plat_mem_setup(void);
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#else
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static inline void ar5312_arch_init_irq(void) {}
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static inline void ar5312_plat_time_init(void) {}
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static inline void ar5312_plat_mem_setup(void) {}
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@ -11,6 +11,29 @@
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#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
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#define __ASM_MACH_ATH25_AR5312_REGS_H
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/*
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* IRQs
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*/
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#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
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#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
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#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
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#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
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#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
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/*
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* Miscellaneous interrupts, which share IP6.
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*/
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#define AR5312_MISC_IRQ_TIMER 0
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#define AR5312_MISC_IRQ_AHB_PROC 1
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#define AR5312_MISC_IRQ_AHB_DMA 2
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#define AR5312_MISC_IRQ_GPIO 3
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#define AR5312_MISC_IRQ_UART0 4
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#define AR5312_MISC_IRQ_UART0_DMA 5
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#define AR5312_MISC_IRQ_WATCHDOG 6
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#define AR5312_MISC_IRQ_LOCAL 7
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#define AR5312_MISC_IRQ_SPI 8
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#define AR5312_MISC_IRQ_COUNT 9
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/*
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* Address Map
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*
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@ -20,6 +20,8 @@
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#include "ar5312.h"
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#include "ar2315.h"
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void (*ath25_irq_dispatch)(void);
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static void ath25_halt(void)
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{
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local_irq_disable();
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@ -42,6 +44,7 @@ void __init plat_mem_setup(void)
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asmlinkage void plat_irq_dispatch(void)
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{
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ath25_irq_dispatch();
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}
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void __init plat_time_init(void)
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@ -61,4 +64,10 @@ void __init arch_init_irq(void)
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{
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clear_c0_status(ST0_IM);
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mips_cpu_irq_init();
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/* Initialize interrupt controllers */
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if (is_ar5312())
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ar5312_arch_init_irq();
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else
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ar2315_arch_init_irq();
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}
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@ -5,6 +5,10 @@
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#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
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#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
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extern void (*ath25_irq_dispatch)(void);
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static inline bool is_ar2315(void)
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{
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return (current_cpu_data.cputype == CPU_4KEC);
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