LX2160A TMU support for 5.5:
- Add TMU (Thermal Monitoring Unit) device node to enable thermal
support on LX2160A SoC.
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Merge tag 'imx-dt64-tmu-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
LX2160A TMU support for 5.5:
- Add TMU (Thermal Monitoring Unit) device node to enable thermal
support on LX2160A SoC.
* tag 'imx-dt64-tmu-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: lx2160a: add tmu device node
ARM: imx_v6_v7_defconfig: Enable CONFIG_DRM_MSM
arm64: dts: imx8mn: Use correct clock for usdhc's ipg clk
arm64: dts: imx8mm: Use correct clock for usdhc's ipg clk
arm64: dts: imx8mq: Use correct clock for usdhc's ipg clk
ARM: dts: imx7s: Correct GPT's ipg clock source
ARM: dts: vf610-zii-scu4-aib: Specify 'i2c-mux-idle-disconnect'
ARM: dts: imx6q-logicpd: Re-Enable SNVS power key
arm64: dts: lx2160a: Correct CPU core idle state name
arm64: dts: zii-ultra: fix ARM regulator states
soc: imx: imx-scu: Getting UID from SCU should have response
Link: https://lore.kernel.org/r/20191105150315.15477-6-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
17795bf9aa
|
|
@ -207,6 +207,10 @@
|
|||
vin-supply = <&sw1c_reg>;
|
||||
};
|
||||
|
||||
&snvs_poweroff {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
|
|
|||
|
|
@ -448,7 +448,7 @@
|
|||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
||||
reg = <0x302d0000 0x10000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_CLK_DUMMY>,
|
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clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
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<&clks IMX7D_GPT1_ROOT_CLK>;
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clock-names = "ipg", "per";
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};
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|
|
@ -457,7 +457,7 @@
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compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
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reg = <0x302e0000 0x10000>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_CLK_DUMMY>,
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clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
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<&clks IMX7D_GPT2_ROOT_CLK>;
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clock-names = "ipg", "per";
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status = "disabled";
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|
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@ -467,7 +467,7 @@
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compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
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reg = <0x302f0000 0x10000>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_CLK_DUMMY>,
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clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
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<&clks IMX7D_GPT3_ROOT_CLK>;
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clock-names = "ipg", "per";
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status = "disabled";
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|
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@ -477,7 +477,7 @@
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compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
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reg = <0x30300000 0x10000>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_CLK_DUMMY>,
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clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
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<&clks IMX7D_GPT4_ROOT_CLK>;
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clock-names = "ipg", "per";
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status = "disabled";
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@ -592,6 +592,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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i2c-mux-idle-disconnect;
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sff0_i2c: i2c@1 {
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#address-cells = <1>;
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@ -630,6 +631,7 @@
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reg = <0x71>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-mux-idle-disconnect;
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sff5_i2c: i2c@1 {
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#address-cells = <1>;
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@ -276,6 +276,7 @@ CONFIG_VIDEO_OV5640=m
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CONFIG_VIDEO_OV5645=m
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CONFIG_IMX_IPUV3_CORE=y
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CONFIG_DRM=y
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CONFIG_DRM_MSM=y
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CONFIG_DRM_PANEL_LVDS=y
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CONFIG_DRM_PANEL_SIMPLE=y
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CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
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@ -6,6 +6,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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/memreserve/ 0x80000000 0x00010000;
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@ -20,7 +21,7 @@
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#size-cells = <0>;
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// 8 clusters having 2 Cortex-A72 cores each
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cpu@0 {
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -33,10 +34,11 @@
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
|
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next-level-cache = <&cluster0_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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|
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cpu@1 {
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -49,10 +51,11 @@
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster0_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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|
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cpu@100 {
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cpu100: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -65,10 +68,11 @@
|
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster1_l2>;
|
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cpu-idle-states = <&cpu_pw20>;
|
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cpu-idle-states = <&cpu_pw15>;
|
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#cooling-cells = <2>;
|
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};
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|
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cpu@101 {
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cpu101: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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|
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@ -81,10 +85,11 @@
|
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster1_l2>;
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cpu-idle-states = <&cpu_pw20>;
|
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@200 {
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cpu200: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -97,10 +102,11 @@
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster2_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@201 {
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cpu201: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -113,10 +119,11 @@
|
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster2_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@300 {
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cpu300: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -129,10 +136,11 @@
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster3_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
|
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};
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|
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cpu@301 {
|
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cpu301: cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -145,10 +153,11 @@
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster3_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@400 {
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cpu400: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -161,10 +170,11 @@
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster4_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@401 {
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cpu401: cpu@401 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -177,10 +187,11 @@
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster4_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@500 {
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cpu500: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -193,10 +204,11 @@
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster5_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@501 {
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cpu501: cpu@501 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -209,10 +221,11 @@
|
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster5_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@600 {
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cpu600: cpu@600 {
|
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -225,10 +238,11 @@
|
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i-cache-line-size = <64>;
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i-cache-sets = <192>;
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next-level-cache = <&cluster6_l2>;
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cpu-idle-states = <&cpu_pw20>;
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cpu-idle-states = <&cpu_pw15>;
|
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#cooling-cells = <2>;
|
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};
|
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|
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cpu@601 {
|
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cpu601: cpu@601 {
|
||||
device_type = "cpu";
|
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compatible = "arm,cortex-a72";
|
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enable-method = "psci";
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|
|
@ -241,10 +255,11 @@
|
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i-cache-line-size = <64>;
|
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i-cache-sets = <192>;
|
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next-level-cache = <&cluster6_l2>;
|
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cpu-idle-states = <&cpu_pw20>;
|
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cpu-idle-states = <&cpu_pw15>;
|
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#cooling-cells = <2>;
|
||||
};
|
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|
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cpu@700 {
|
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cpu700: cpu@700 {
|
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device_type = "cpu";
|
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compatible = "arm,cortex-a72";
|
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enable-method = "psci";
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|
|
@ -257,10 +272,11 @@
|
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i-cache-line-size = <64>;
|
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i-cache-sets = <192>;
|
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next-level-cache = <&cluster7_l2>;
|
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cpu-idle-states = <&cpu_pw20>;
|
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cpu-idle-states = <&cpu_pw15>;
|
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#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu@701 {
|
||||
cpu701: cpu@701 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
|
|
@ -273,7 +289,8 @@
|
|||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster7_l2>;
|
||||
cpu-idle-states = <&cpu_pw20>;
|
||||
cpu-idle-states = <&cpu_pw15>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cluster0_l2: l2-cache0 {
|
||||
|
|
@ -340,9 +357,9 @@
|
|||
cache-level = <2>;
|
||||
};
|
||||
|
||||
cpu_pw20: cpu-pw20 {
|
||||
cpu_pw15: cpu-pw15 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PW20";
|
||||
idle-state-name = "PW15";
|
||||
arm,psci-suspend-param = <0x0>;
|
||||
entry-latency-us = <2000>;
|
||||
exit-latency-us = <2000>;
|
||||
|
|
@ -418,6 +435,51 @@
|
|||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
core_thermal1: core-thermal1 {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 0>;
|
||||
|
||||
trips {
|
||||
core_cluster_alert: core-cluster-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
core_cluster_crit: core-cluster-crit {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&core_cluster_alert>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -478,6 +540,20 @@
|
|||
little-endian;
|
||||
};
|
||||
|
||||
tmu: tmu@1f80000 {
|
||||
compatible = "fsl,qoriq-tmu";
|
||||
reg = <0x0 0x1f80000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,tmu-range = <0x800000e6 0x8001017d>;
|
||||
fsl,tmu-calibration =
|
||||
/* Calibration data group 1 */
|
||||
<0x00000000 0x00000035
|
||||
/* Calibration data group 2 */
|
||||
0x00010001 0x00000154>;
|
||||
little-endian;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
i2c0: i2c@2000000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -697,7 +697,7 @@
|
|||
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MM_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
|
|
@ -711,7 +711,7 @@
|
|||
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MM_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
|
|
@ -725,7 +725,7 @@
|
|||
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b60000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MM_CLK_USDHC3_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
|
|
|
|||
|
|
@ -593,7 +593,7 @@
|
|||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
|
|
@ -607,7 +607,7 @@
|
|||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
|
|
@ -621,7 +621,7 @@
|
|||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b60000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC3_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
|
|
|
|||
|
|
@ -98,8 +98,8 @@
|
|||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
|
||||
states = <1000000 0x0
|
||||
900000 0x1>;
|
||||
states = <1000000 0x1
|
||||
900000 0x0>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -864,7 +864,7 @@
|
|||
"fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
|
|
@ -879,7 +879,7 @@
|
|||
"fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ static ssize_t soc_uid_show(struct device *dev,
|
|||
hdr->func = IMX_SC_MISC_FUNC_UNIQUE_ID;
|
||||
hdr->size = 1;
|
||||
|
||||
ret = imx_scu_call_rpc(soc_ipc_handle, &msg, false);
|
||||
ret = imx_scu_call_rpc(soc_ipc_handle, &msg, true);
|
||||
if (ret) {
|
||||
pr_err("%s: get soc uid failed, ret %d\n", __func__, ret);
|
||||
return ret;
|
||||
|
|
|
|||
Loading…
Reference in a new issue