clk: sunxi-ng: mux: Increase fixed pre-divider div size
Some clocks have a predivider value that is larger than what u8 can store. One such example is the OUT clk found on A20/A31, which has a /750 pre-divider on one of the osc24M parents. Increase the size of the div field to u16. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -18,7 +18,7 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
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int parent_index,
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unsigned long *parent_rate)
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{
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u8 prediv = 1;
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u16 prediv = 1;
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u32 reg;
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if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
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@ -11,7 +11,7 @@ struct ccu_mux_internal {
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struct {
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u8 index;
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u8 div;
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u16 div;
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} fixed_prediv;
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struct {
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