perf: riscv: preliminary RISC-V support
This patch provide a basic PMU, riscv_base_pmu, which supports two general hardware event, instructions and cycles. Furthermore, this PMU serves as a reference implementation to ease the portings in the future. riscv_base_pmu should be able to run on any RISC-V machine that conforms to the Priv-Spec. Note that the latest qemu model hasn't fully support a proper behavior of Priv-Spec 1.10 yet, but work around should be easy with very small fixes. Please check https://github.com/riscv/riscv-qemu/pull/115 for future updates. Cc: Nick Hu <nickhu@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Signed-off-by: Alan Kao <alankao@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>hifive-unleashed-5.1
Alan Kao
Palmer Dabbelt
parent
29dcea8877
commit
178e9fc47a
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@ -25,6 +25,7 @@ config RISCV
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select HAVE_DMA_API_DEBUG
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select HAVE_DMA_CONTIGUOUS
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select HAVE_GENERIC_DMA_COHERENT
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select HAVE_PERF_EVENTS
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select IRQ_DOMAIN
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select NO_BOOTMEM
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select RISCV_ISA_A if SMP
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@ -198,6 +199,19 @@ config RISCV_ISA_C
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config RISCV_ISA_A
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def_bool y
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menu "supported PMU type"
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depends on PERF_EVENTS
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config RISCV_BASE_PMU
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bool "Base Performance Monitoring Unit"
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def_bool y
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help
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A base PMU that serves as a reference implementation and has limited
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feature of perf. It can run on any RISC-V machines so serves as the
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fallback, but this option can also be disable to reduce kernel size.
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endmenu
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endmenu
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menu "Kernel type"
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@ -25,6 +25,7 @@ generic-y += kdebug.h
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generic-y += kmap_types.h
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generic-y += kvm_para.h
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generic-y += local.h
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generic-y += local64.h
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generic-y += mm-arch-hooks.h
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generic-y += mman.h
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generic-y += module.h
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@ -0,0 +1,84 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 SiFive
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* Copyright (C) 2018 Andes Technology Corporation
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*
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*/
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#ifndef _ASM_RISCV_PERF_EVENT_H
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#define _ASM_RISCV_PERF_EVENT_H
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#include <linux/perf_event.h>
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#include <linux/ptrace.h>
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#define RISCV_BASE_COUNTERS 2
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/*
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* The RISCV_MAX_COUNTERS parameter should be specified.
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*/
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#ifdef CONFIG_RISCV_BASE_PMU
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#define RISCV_MAX_COUNTERS 2
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#endif
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#ifndef RISCV_MAX_COUNTERS
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#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU."
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#endif
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/*
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* These are the indexes of bits in counteren register *minus* 1,
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* except for cycle. It would be coherent if it can directly mapped
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* to counteren bit definition, but there is a *time* register at
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* counteren[1]. Per-cpu structure is scarce resource here.
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*
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* According to the spec, an implementation can support counter up to
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* mhpmcounter31, but many high-end processors has at most 6 general
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* PMCs, we give the definition to MHPMCOUNTER8 here.
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*/
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#define RISCV_PMU_CYCLE 0
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#define RISCV_PMU_INSTRET 1
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#define RISCV_PMU_MHPMCOUNTER3 2
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#define RISCV_PMU_MHPMCOUNTER4 3
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#define RISCV_PMU_MHPMCOUNTER5 4
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#define RISCV_PMU_MHPMCOUNTER6 5
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#define RISCV_PMU_MHPMCOUNTER7 6
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#define RISCV_PMU_MHPMCOUNTER8 7
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#define RISCV_OP_UNSUPP (-EOPNOTSUPP)
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struct cpu_hw_events {
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/* # currently enabled events*/
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int n_events;
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/* currently enabled events */
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struct perf_event *events[RISCV_MAX_COUNTERS];
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/* vendor-defined PMU data */
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void *platform;
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};
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struct riscv_pmu {
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struct pmu *pmu;
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/* generic hw/cache events table */
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const int *hw_events;
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const int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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/* method used to map hw/cache events */
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int (*map_hw_event)(u64 config);
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int (*map_cache_event)(u64 config);
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/* max generic hw events in map */
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int max_events;
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/* number total counters, 2(base) + x(general) */
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int num_counters;
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/* the width of the counter */
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int counter_width;
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/* vendor-defined PMU features */
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void *platform;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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int irq;
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};
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#endif /* _ASM_RISCV_PERF_EVENT_H */
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@ -39,4 +39,6 @@ obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
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obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
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obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o
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obj-$(CONFIG_PERF_EVENTS) += perf_event.o
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clean:
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@ -0,0 +1,485 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
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* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
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* Copyright (C) 2009 Jaswinder Singh Rajput
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* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
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* Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
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* Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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* Copyright (C) 2009 Google, Inc., Stephane Eranian
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* Copyright 2014 Tilera Corporation. All Rights Reserved.
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* Copyright (C) 2018 Andes Technology Corporation
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*
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* Perf_events support for RISC-V platforms.
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*
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* Since the spec. (as of now, Priv-Spec 1.10) does not provide enough
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* functionality for perf event to fully work, this file provides
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* the very basic framework only.
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*
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* For platform portings, please check Documentations/riscv/pmu.txt.
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*
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* The Copyright line includes x86 and tile ones.
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*/
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#include <linux/kprobes.h>
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#include <linux/kernel.h>
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#include <linux/kdebug.h>
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#include <linux/mutex.h>
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#include <linux/bitmap.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/perf_event.h>
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#include <linux/atomic.h>
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#include <linux/of.h>
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#include <asm/perf_event.h>
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static const struct riscv_pmu *riscv_pmu __read_mostly;
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static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
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/*
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* Hardware & cache maps and their methods
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*/
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static const int riscv_hw_event_map[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = RISCV_PMU_CYCLE,
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[PERF_COUNT_HW_INSTRUCTIONS] = RISCV_PMU_INSTRET,
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[PERF_COUNT_HW_CACHE_REFERENCES] = RISCV_OP_UNSUPP,
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[PERF_COUNT_HW_CACHE_MISSES] = RISCV_OP_UNSUPP,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = RISCV_OP_UNSUPP,
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[PERF_COUNT_HW_BRANCH_MISSES] = RISCV_OP_UNSUPP,
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[PERF_COUNT_HW_BUS_CYCLES] = RISCV_OP_UNSUPP,
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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static const int riscv_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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[C(L1D)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
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[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
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},
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},
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};
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static int riscv_map_hw_event(u64 config)
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{
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if (config >= riscv_pmu->max_events)
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return -EINVAL;
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return riscv_pmu->hw_events[config];
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}
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int riscv_map_cache_decode(u64 config, unsigned int *type,
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unsigned int *op, unsigned int *result)
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{
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return -ENOENT;
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}
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static int riscv_map_cache_event(u64 config)
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{
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unsigned int type, op, result;
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int err = -ENOENT;
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int code;
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err = riscv_map_cache_decode(config, &type, &op, &result);
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if (!riscv_pmu->cache_events || err)
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return err;
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if (type >= PERF_COUNT_HW_CACHE_MAX ||
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op >= PERF_COUNT_HW_CACHE_OP_MAX ||
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result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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code = (*riscv_pmu->cache_events)[type][op][result];
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if (code == RISCV_OP_UNSUPP)
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return -EINVAL;
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return code;
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}
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/*
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* Low-level functions: reading/writing counters
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*/
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static inline u64 read_counter(int idx)
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{
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u64 val = 0;
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switch (idx) {
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case RISCV_PMU_CYCLE:
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val = csr_read(cycle);
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break;
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case RISCV_PMU_INSTRET:
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val = csr_read(instret);
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break;
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default:
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WARN_ON_ONCE(idx < 0 || idx > RISCV_MAX_COUNTERS);
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return -EINVAL;
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}
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return val;
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}
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static inline void write_counter(int idx, u64 value)
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{
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/* currently not supported */
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WARN_ON_ONCE(1);
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}
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/*
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* pmu->read: read and update the counter
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*
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* Other architectures' implementation often have a xxx_perf_event_update
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* routine, which can return counter values when called in the IRQ, but
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* return void when being called by the pmu->read method.
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*/
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static void riscv_pmu_read(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 prev_raw_count, new_raw_count;
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u64 oldval;
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int idx = hwc->idx;
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u64 delta;
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do {
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = read_counter(idx);
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oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count);
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} while (oldval != prev_raw_count);
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/*
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* delta is the value to update the counter we maintain in the kernel.
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*/
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delta = (new_raw_count - prev_raw_count) &
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((1ULL << riscv_pmu->counter_width) - 1);
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local64_add(delta, &event->count);
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/*
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* Something like local64_sub(delta, &hwc->period_left) here is
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* needed if there is an interrupt for perf.
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*/
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}
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/*
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* State transition functions:
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*
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* stop()/start() & add()/del()
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*/
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/*
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* pmu->stop: stop the counter
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*/
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static void riscv_pmu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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hwc->state |= PERF_HES_STOPPED;
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if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
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riscv_pmu->pmu->read(event);
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hwc->state |= PERF_HES_UPTODATE;
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}
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}
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/*
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* pmu->start: start the event.
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*/
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static void riscv_pmu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
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return;
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if (flags & PERF_EF_RELOAD) {
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WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
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/*
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* Set the counter to the period to the next interrupt here,
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* if you have any.
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*/
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}
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hwc->state = 0;
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perf_event_update_userpage(event);
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/*
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* Since we cannot write to counters, this serves as an initialization
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* to the delta-mechanism in pmu->read(); otherwise, the delta would be
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* wrong when pmu->read is called for the first time.
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*/
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local64_set(&hwc->prev_count, read_counter(hwc->idx));
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}
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/*
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* pmu->add: add the event to PMU.
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*/
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static int riscv_pmu_add(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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if (cpuc->n_events == riscv_pmu->num_counters)
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return -ENOSPC;
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/*
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* We don't have general conunters, so no binding-event-to-counter
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* process here.
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*
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* Indexing using hwc->config generally not works, since config may
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* contain extra information, but here the only info we have in
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* hwc->config is the event index.
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*/
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hwc->idx = hwc->config;
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cpuc->events[hwc->idx] = event;
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cpuc->n_events++;
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hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
|
||||
|
||||
if (flags & PERF_EF_START)
|
||||
riscv_pmu->pmu->start(event, PERF_EF_RELOAD);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* pmu->del: delete the event from PMU.
|
||||
*/
|
||||
static void riscv_pmu_del(struct perf_event *event, int flags)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
||||
cpuc->events[hwc->idx] = NULL;
|
||||
cpuc->n_events--;
|
||||
riscv_pmu->pmu->stop(event, PERF_EF_UPDATE);
|
||||
perf_event_update_userpage(event);
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupt: a skeletion for reference.
|
||||
*/
|
||||
|
||||
static DEFINE_MUTEX(pmc_reserve_mutex);
|
||||
|
||||
irqreturn_t riscv_base_pmu_handle_irq(int irq_num, void *dev)
|
||||
{
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static int reserve_pmc_hardware(void)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
mutex_lock(&pmc_reserve_mutex);
|
||||
if (riscv_pmu->irq >= 0 && riscv_pmu->handle_irq) {
|
||||
err = request_irq(riscv_pmu->irq, riscv_pmu->handle_irq,
|
||||
IRQF_PERCPU, "riscv-base-perf", NULL);
|
||||
}
|
||||
mutex_unlock(&pmc_reserve_mutex);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
void release_pmc_hardware(void)
|
||||
{
|
||||
mutex_lock(&pmc_reserve_mutex);
|
||||
if (riscv_pmu->irq >= 0)
|
||||
free_irq(riscv_pmu->irq, NULL);
|
||||
mutex_unlock(&pmc_reserve_mutex);
|
||||
}
|
||||
|
||||
/*
|
||||
* Event Initialization/Finalization
|
||||
*/
|
||||
|
||||
static atomic_t riscv_active_events = ATOMIC_INIT(0);
|
||||
|
||||
static void riscv_event_destroy(struct perf_event *event)
|
||||
{
|
||||
if (atomic_dec_return(&riscv_active_events) == 0)
|
||||
release_pmc_hardware();
|
||||
}
|
||||
|
||||
static int riscv_event_init(struct perf_event *event)
|
||||
{
|
||||
struct perf_event_attr *attr = &event->attr;
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int err;
|
||||
int code;
|
||||
|
||||
if (atomic_inc_return(&riscv_active_events) == 1) {
|
||||
err = reserve_pmc_hardware();
|
||||
|
||||
if (err) {
|
||||
pr_warn("PMC hardware not available\n");
|
||||
atomic_dec(&riscv_active_events);
|
||||
return -EBUSY;
|
||||
}
|
||||
}
|
||||
|
||||
switch (event->attr.type) {
|
||||
case PERF_TYPE_HARDWARE:
|
||||
code = riscv_pmu->map_hw_event(attr->config);
|
||||
break;
|
||||
case PERF_TYPE_HW_CACHE:
|
||||
code = riscv_pmu->map_cache_event(attr->config);
|
||||
break;
|
||||
case PERF_TYPE_RAW:
|
||||
return -EOPNOTSUPP;
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
event->destroy = riscv_event_destroy;
|
||||
if (code < 0) {
|
||||
event->destroy(event);
|
||||
return code;
|
||||
}
|
||||
|
||||
/*
|
||||
* idx is set to -1 because the index of a general event should not be
|
||||
* decided until binding to some counter in pmu->add().
|
||||
*
|
||||
* But since we don't have such support, later in pmu->add(), we just
|
||||
* use hwc->config as the index instead.
|
||||
*/
|
||||
hwc->config = code;
|
||||
hwc->idx = -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialization
|
||||
*/
|
||||
|
||||
static struct pmu min_pmu = {
|
||||
.name = "riscv-base",
|
||||
.event_init = riscv_event_init,
|
||||
.add = riscv_pmu_add,
|
||||
.del = riscv_pmu_del,
|
||||
.start = riscv_pmu_start,
|
||||
.stop = riscv_pmu_stop,
|
||||
.read = riscv_pmu_read,
|
||||
};
|
||||
|
||||
static const struct riscv_pmu riscv_base_pmu = {
|
||||
.pmu = &min_pmu,
|
||||
.max_events = ARRAY_SIZE(riscv_hw_event_map),
|
||||
.map_hw_event = riscv_map_hw_event,
|
||||
.hw_events = riscv_hw_event_map,
|
||||
.map_cache_event = riscv_map_cache_event,
|
||||
.cache_events = &riscv_cache_event_map,
|
||||
.counter_width = 63,
|
||||
.num_counters = RISCV_BASE_COUNTERS + 0,
|
||||
.handle_irq = &riscv_base_pmu_handle_irq,
|
||||
|
||||
/* This means this PMU has no IRQ. */
|
||||
.irq = -1,
|
||||
};
|
||||
|
||||
static const struct of_device_id riscv_pmu_of_ids[] = {
|
||||
{.compatible = "riscv,base-pmu", .data = &riscv_base_pmu},
|
||||
{ /* sentinel value */ }
|
||||
};
|
||||
|
||||
int __init init_hw_perf_events(void)
|
||||
{
|
||||
struct device_node *node = of_find_node_by_type(NULL, "pmu");
|
||||
const struct of_device_id *of_id;
|
||||
|
||||
riscv_pmu = &riscv_base_pmu;
|
||||
|
||||
if (node) {
|
||||
of_id = of_match_node(riscv_pmu_of_ids, node);
|
||||
|
||||
if (of_id)
|
||||
riscv_pmu = of_id->data;
|
||||
}
|
||||
|
||||
perf_pmu_register(riscv_pmu->pmu, "cpu", PERF_TYPE_RAW);
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(init_hw_perf_events);
|
||||
Loading…
Reference in New Issue