redonkable/alistair23-linux
redonkable/alistair23-linux
1
0
Fork 0
Code Releases Activity

clk: imx: Rename sccg and frac pll register to suggest clk_hw

Browse source 
Renaming the imx_clk_frac_pll and imx_clk_sccg_pll register functions to
imx_clk_hw_frac_pll, respectively imx_clk_hw_sccg_pll to be more obvious
that they are clk_hw based.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Abel Vesa 2019-12-11 11:25:46 +02:00 committed by Shawn Guo
parent 7c3f951a97
commit 179c1f7c7a
3 changed files with 16 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
drivers/clk/imx/clk-frac-pll.c
View file

@ -201,8 +201,9 @@ static const struct clk_ops clk_frac_pll_ops = {
.set_rate = clk_pll_set_rate,
};
struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
void __iomem *base)
struct clk_hw *imx_clk_hw_frac_pll(const char *name,
const char *parent_name,
void __iomem *base)
{
struct clk_init_data init;
struct clk_frac_pll *pll;
@ -230,5 +231,5 @@ struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
return ERR_PTR(ret);
}
return hw->clk;
return hw;
}

4
drivers/clk/imx/clk-sscg-pll.c
View file

@ -506,7 +506,7 @@ static const struct clk_ops clk_sscg_pll_ops = {
.determine_rate = clk_sscg_pll_determine_rate,
};
struct clk *imx_clk_sscg_pll(const char *name,
struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
const char * const *parent_names,
u8 num_parents,
u8 parent, u8 bypass1, u8 bypass2,
@ -545,5 +545,5 @@ struct clk *imx_clk_sscg_pll(const char *name,
return ERR_PTR(ret);
}
return hw->clk;
return hw;
}

12
drivers/clk/imx/clk.h
View file

@ -116,6 +116,14 @@ extern struct imx_pll14xx_clk imx_1443x_dram_pll;
#define imx_clk_pllv2(name, parent, base) \
to_clk(imx_clk_hw_pllv2(name, parent, base))
#define imx_clk_frac_pll(name, parent_name, base) \
to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
#define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\
bypass1, bypass2, base, flags) \
to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
bypass1, bypass2, base, flags))
struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
@ -125,10 +133,10 @@ struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
void __iomem *base);
struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
void __iomem *base);
struct clk *imx_clk_sscg_pll(const char *name,
struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
const char * const *parent_names,
u8 num_parents,
u8 parent, u8 bypass1, u8 bypass2,