i2c-cht-wc: Add Intel Cherry Trail Whiskey Cove SMBUS controller driver
The Intel Cherry Trail Whiskey Cove PMIC does not contain a builtin battery charger, instead boards with this PMIC use an external TI bq24292i charger IC, which is connected to a SMBUS controller built into the PMIC. This commit adds an i2c-bus driver for the PMIC's builtin SMBUS controller. The probe function for this i2c-bus will also register an i2c-client for the TI bq24292i charger after the i2c-bus has been registered. Note that several device-properties are set on the client-device to tell the bq24190 power-supply driver to integrate the Whiskey Cove PMIC and e.g. use the PMIC's BC1.2 detection (through extcon) to determine the maximum input current. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>hifive-unleashed-5.1
Hans de Goede
Wolfram Sang
parent
0a1c7959ac
commit
17a924bfe0
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@ -189,6 +189,14 @@ config I2C_PIIX4
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This driver can also be built as a module. If so, the module
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will be called i2c-piix4.
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config I2C_CHT_WC
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tristate "Intel Cherry Trail Whiskey Cove PMIC smbus controller"
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depends on INTEL_SOC_PMIC_CHTWC
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help
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If you say yes to this option, support will be included for the
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SMBus controller found in the Intel Cherry Trail Whiskey Cove PMIC
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found on some Intel Cherry Trail systems.
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config I2C_NFORCE2
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tristate "Nvidia nForce2, nForce3 and nForce4"
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depends on PCI
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@ -12,6 +12,7 @@ obj-$(CONFIG_I2C_ALI15X3) += i2c-ali15x3.o
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obj-$(CONFIG_I2C_AMD756) += i2c-amd756.o
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obj-$(CONFIG_I2C_AMD756_S4882) += i2c-amd756-s4882.o
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obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o
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obj-$(CONFIG_I2C_CHT_WC) += i2c-cht-wc.o
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obj-$(CONFIG_I2C_I801) += i2c-i801.o
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obj-$(CONFIG_I2C_ISCH) += i2c-isch.o
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obj-$(CONFIG_I2C_ISMT) += i2c-ismt.o
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@ -0,0 +1,337 @@
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/*
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* Intel CHT Whiskey Cove PMIC I2C Master driver
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* Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
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* Copyright (C) 2011 - 2014 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define CHT_WC_I2C_CTRL 0x5e24
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#define CHT_WC_I2C_CTRL_WR BIT(0)
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#define CHT_WC_I2C_CTRL_RD BIT(1)
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#define CHT_WC_I2C_CLIENT_ADDR 0x5e25
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#define CHT_WC_I2C_REG_OFFSET 0x5e26
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#define CHT_WC_I2C_WRDATA 0x5e27
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#define CHT_WC_I2C_RDDATA 0x5e28
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#define CHT_WC_EXTCHGRIRQ 0x6e0a
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#define CHT_WC_EXTCHGRIRQ_CLIENT_IRQ BIT(0)
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#define CHT_WC_EXTCHGRIRQ_WRITE_IRQ BIT(1)
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#define CHT_WC_EXTCHGRIRQ_READ_IRQ BIT(2)
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#define CHT_WC_EXTCHGRIRQ_NACK_IRQ BIT(3)
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#define CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK ((u8)GENMASK(3, 1))
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#define CHT_WC_EXTCHGRIRQ_MSK 0x6e17
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struct cht_wc_i2c_adap {
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struct i2c_adapter adapter;
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wait_queue_head_t wait;
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struct irq_chip irqchip;
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struct mutex irqchip_lock;
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struct regmap *regmap;
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struct irq_domain *irq_domain;
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struct i2c_client *client;
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int client_irq;
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u8 irq_mask;
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u8 old_irq_mask;
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bool nack;
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bool done;
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};
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static irqreturn_t cht_wc_i2c_adap_thread_handler(int id, void *data)
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{
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struct cht_wc_i2c_adap *adap = data;
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int ret, reg;
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/* Read IRQs */
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ret = regmap_read(adap->regmap, CHT_WC_EXTCHGRIRQ, ®);
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if (ret) {
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dev_err(&adap->adapter.dev, "Error reading extchgrirq reg\n");
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return IRQ_NONE;
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}
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reg &= ~adap->irq_mask;
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/*
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* Immediately ack IRQs, so that if new IRQs arrives while we're
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* handling the previous ones our irq will re-trigger when we're done.
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*/
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ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, reg);
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if (ret)
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dev_err(&adap->adapter.dev, "Error writing extchgrirq reg\n");
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/*
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* Do NOT use handle_nested_irq here, the client irq handler will
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* likely want to do i2c transfers and the i2c controller uses this
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* interrupt handler as well, so running the client irq handler from
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* this thread will cause things to lock up.
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*/
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if (reg & CHT_WC_EXTCHGRIRQ_CLIENT_IRQ) {
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/*
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* generic_handle_irq expects local IRQs to be disabled
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* as normally it is called from interrupt context.
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*/
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local_irq_disable();
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generic_handle_irq(adap->client_irq);
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local_irq_enable();
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}
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if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) {
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adap->nack = !!(reg & CHT_WC_EXTCHGRIRQ_NACK_IRQ);
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adap->done = true;
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wake_up(&adap->wait);
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}
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return IRQ_HANDLED;
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}
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static u32 cht_wc_i2c_adap_master_func(struct i2c_adapter *adap)
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{
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/* This i2c adapter only supports SMBUS byte transfers */
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return I2C_FUNC_SMBUS_BYTE_DATA;
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}
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static int cht_wc_i2c_adap_smbus_xfer(struct i2c_adapter *_adap, u16 addr,
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unsigned short flags, char read_write,
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u8 command, int size,
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union i2c_smbus_data *data)
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{
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struct cht_wc_i2c_adap *adap = i2c_get_adapdata(_adap);
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int ret, reg;
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adap->nack = false;
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adap->done = false;
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ret = regmap_write(adap->regmap, CHT_WC_I2C_CLIENT_ADDR, addr);
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if (ret)
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return ret;
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if (read_write == I2C_SMBUS_WRITE) {
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ret = regmap_write(adap->regmap, CHT_WC_I2C_WRDATA, data->byte);
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if (ret)
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return ret;
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}
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ret = regmap_write(adap->regmap, CHT_WC_I2C_REG_OFFSET, command);
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if (ret)
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return ret;
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ret = regmap_write(adap->regmap, CHT_WC_I2C_CTRL,
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(read_write == I2C_SMBUS_WRITE) ?
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CHT_WC_I2C_CTRL_WR : CHT_WC_I2C_CTRL_RD);
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if (ret)
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return ret;
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/* 3 second timeout, during cable plug the PMIC responds quite slow */
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ret = wait_event_timeout(adap->wait, adap->done, 3 * HZ);
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if (ret == 0)
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return -ETIMEDOUT;
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if (adap->nack)
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return -EIO;
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if (read_write == I2C_SMBUS_READ) {
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ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, ®);
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if (ret)
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return ret;
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data->byte = reg;
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}
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return 0;
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}
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static const struct i2c_algorithm cht_wc_i2c_adap_algo = {
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.functionality = cht_wc_i2c_adap_master_func,
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.smbus_xfer = cht_wc_i2c_adap_smbus_xfer,
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};
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/**** irqchip for the client connected to the extchgr i2c adapter ****/
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static void cht_wc_i2c_irq_lock(struct irq_data *data)
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{
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struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
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mutex_lock(&adap->irqchip_lock);
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}
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static void cht_wc_i2c_irq_sync_unlock(struct irq_data *data)
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{
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struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
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int ret;
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if (adap->irq_mask != adap->old_irq_mask) {
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ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK,
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adap->irq_mask);
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if (ret == 0)
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adap->old_irq_mask = adap->irq_mask;
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else
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dev_err(&adap->adapter.dev, "Error writing EXTCHGRIRQ_MSK\n");
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}
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mutex_unlock(&adap->irqchip_lock);
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}
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static void cht_wc_i2c_irq_enable(struct irq_data *data)
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{
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struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
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adap->irq_mask &= ~CHT_WC_EXTCHGRIRQ_CLIENT_IRQ;
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}
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static void cht_wc_i2c_irq_disable(struct irq_data *data)
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{
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struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data);
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adap->irq_mask |= CHT_WC_EXTCHGRIRQ_CLIENT_IRQ;
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}
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static const struct irq_chip cht_wc_i2c_irq_chip = {
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.irq_bus_lock = cht_wc_i2c_irq_lock,
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.irq_bus_sync_unlock = cht_wc_i2c_irq_sync_unlock,
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.irq_disable = cht_wc_i2c_irq_disable,
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.irq_enable = cht_wc_i2c_irq_enable,
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.name = "cht_wc_ext_chrg_irq_chip",
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};
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static const struct property_entry bq24190_props[] = {
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PROPERTY_ENTRY_STRING("extcon-name", "cht_wcove_pwrsrc"),
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PROPERTY_ENTRY_BOOL("omit-battery-class"),
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PROPERTY_ENTRY_BOOL("disable-reset"),
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{ }
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};
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static int cht_wc_i2c_adap_i2c_probe(struct platform_device *pdev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
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struct cht_wc_i2c_adap *adap;
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struct i2c_board_info board_info = {
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.type = "bq24190",
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.addr = 0x6b,
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.properties = bq24190_props,
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};
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int ret, irq;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "Error missing irq resource\n");
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return -EINVAL;
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}
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adap = devm_kzalloc(&pdev->dev, sizeof(*adap), GFP_KERNEL);
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if (!adap)
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return -ENOMEM;
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init_waitqueue_head(&adap->wait);
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mutex_init(&adap->irqchip_lock);
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adap->irqchip = cht_wc_i2c_irq_chip;
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adap->regmap = pmic->regmap;
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adap->adapter.owner = THIS_MODULE;
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adap->adapter.class = I2C_CLASS_HWMON;
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adap->adapter.algo = &cht_wc_i2c_adap_algo;
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strlcpy(adap->adapter.name, "PMIC I2C Adapter",
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sizeof(adap->adapter.name));
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adap->adapter.dev.parent = &pdev->dev;
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/* Clear and activate i2c-adapter interrupts, disable client IRQ */
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adap->old_irq_mask = adap->irq_mask = ~CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK;
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ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, ~adap->irq_mask);
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if (ret)
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return ret;
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ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, adap->irq_mask);
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if (ret)
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return ret;
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/* Alloc and register client IRQ */
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adap->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 1,
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&irq_domain_simple_ops, NULL);
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if (!adap->irq_domain)
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return -ENOMEM;
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adap->client_irq = irq_create_mapping(adap->irq_domain, 0);
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if (!adap->client_irq) {
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ret = -ENOMEM;
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goto remove_irq_domain;
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}
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irq_set_chip_data(adap->client_irq, adap);
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irq_set_chip_and_handler(adap->client_irq, &adap->irqchip,
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handle_simple_irq);
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ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
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cht_wc_i2c_adap_thread_handler,
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IRQF_ONESHOT, "PMIC I2C Adapter", adap);
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if (ret)
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goto remove_irq_domain;
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i2c_set_adapdata(&adap->adapter, adap);
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ret = i2c_add_adapter(&adap->adapter);
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if (ret)
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goto remove_irq_domain;
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board_info.irq = adap->client_irq;
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adap->client = i2c_new_device(&adap->adapter, &board_info);
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if (!adap->client) {
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ret = -ENOMEM;
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goto del_adapter;
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}
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platform_set_drvdata(pdev, adap);
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return 0;
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del_adapter:
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i2c_del_adapter(&adap->adapter);
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remove_irq_domain:
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irq_domain_remove(adap->irq_domain);
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return ret;
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}
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static int cht_wc_i2c_adap_i2c_remove(struct platform_device *pdev)
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{
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struct cht_wc_i2c_adap *adap = platform_get_drvdata(pdev);
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i2c_unregister_device(adap->client);
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i2c_del_adapter(&adap->adapter);
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irq_domain_remove(adap->irq_domain);
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return 0;
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}
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static struct platform_device_id cht_wc_i2c_adap_id_table[] = {
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{ .name = "cht_wcove_ext_chgr" },
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{},
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};
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MODULE_DEVICE_TABLE(platform, cht_wc_i2c_adap_id_table);
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struct platform_driver cht_wc_i2c_adap_driver = {
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.probe = cht_wc_i2c_adap_i2c_probe,
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.remove = cht_wc_i2c_adap_i2c_remove,
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.driver = {
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.name = "cht_wcove_ext_chgr",
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},
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.id_table = cht_wc_i2c_adap_id_table,
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};
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module_platform_driver(cht_wc_i2c_adap_driver);
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MODULE_DESCRIPTION("Intel CHT Whiskey Cove PMIC I2C Master driver");
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MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
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MODULE_LICENSE("GPL");
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