ARM: imx6q: clk: Parent DI clocks to video PLL via di_pre_sel
Route the video PLL to the display interface clocks via the di_pre_sel and di_sel muxes by default. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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@ -445,6 +445,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
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}
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clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
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clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
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clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
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clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
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clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
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clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
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clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
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clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
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/*
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* The gpmi needs 100MHz frequency in the EDO/Sync mode,
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* We can not get the 100MHz from the pll2_pfd0_352m.
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