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drm/amd/pp: Fix pp_sclk/mclk_od not work on smu7 

not update the dpm table with user's setting

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Rex Zhu 2018-10-22 13:27:37 +08:00 committed by Alex Deucher
parent 5be3bb6e92
commit 17c7c7e714
1 changed files with 6 additions and 4 deletions
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10
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
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@ -3588,9 +3588,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
break;
}
if (i >= sclk_table->count)
if (i >= sclk_table->count) {
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
else {
sclk_table->dpm_levels[i-1].value = sclk;
} else {
/* TODO: Check SCLK in DAL's minimum clocks
* in case DeepSleep divider update is required.
*/
@ -3605,9 +3606,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
break;
}
if (i >= mclk_table->count)
if (i >= mclk_table->count) {
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
mclk_table->dpm_levels[i-1].value = mclk;
}
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;