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usb: dwc3: core: define bit 10 of GCTL register 

This bit is necessary for implemeting workaround
for known issue with some revisions of this core.

Signed-off-by: Felipe Balbi <balbi@ti.com>
hifive-unleashed-5.1
Felipe Balbi 2014-02-25 14:08:51 -06:00
parent f3af36511e
commit 183ca11179
1 changed files with 1 additions and 0 deletions
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1
drivers/usb/dwc3/core.h
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@ -157,6 +157,7 @@
#define DWC3_GCTL_PRTCAP_OTG 3
#define DWC3_GCTL_CORESOFTRESET (1 << 11)
#define DWC3_GCTL_SOFITPSYNC (1 << 10)
#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
#define DWC3_GCTL_DISSCRAMBLE (1 << 3)