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drm/amd/powerplay: implement fw related smu interface for iceland. 

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Rex Zhu 2016-08-23 11:58:14 +08:00 committed by Alex Deucher
parent 9c6d495696
commit 18aafc59b1
6 changed files with 2673 additions and 17 deletions
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14
drivers/gpu/drm/amd/powerplay/hwmgr/iceland_powertune.h
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@ -49,20 +49,6 @@ struct iceland_pt_config_reg {
enum iceland_pt_config_reg_type type;
};
struct iceland_pt_defaults
{
uint8_t svi_load_line_en;
uint8_t svi_load_line_vddc;
uint8_t tdc_vddc_throttle_release_limit_perc;
uint8_t tdc_mawt;
uint8_t tdc_waterfall_ctl;
uint8_t dte_ambient_temp_base;
uint32_t display_cac;
uint32_t bamp_temp_gradient;
uint16_t bapmti_r[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
uint16_t bapmti_rc[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
};
void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr);

5
drivers/gpu/drm/amd/powerplay/smumgr/Makefile
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@ -2,8 +2,9 @@
# Makefile for the 'smu manager' sub-component of powerplay.
# It provides the smu management services for the driver.
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o\
polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o smu7_smumgr.o
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
smu7_smumgr.o iceland_smc.o
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))

2576
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c 100644
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File diff suppressed because it is too large Load Diff

40
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.h 100644
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@ -0,0 +1,40 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _ICELAND_SMC_H
#define _ICELAND_SMC_H
#include "smumgr.h"
int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
int iceland_init_smc_table(struct pp_hwmgr *hwmgr);
int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr);
uint32_t iceland_get_offsetof(uint32_t type, uint32_t member);
uint32_t iceland_get_mac_definition(uint32_t value);
int iceland_process_firmware_header(struct pp_hwmgr *hwmgr);
int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr);
#endif

21
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
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@ -35,6 +35,7 @@
#include "smu/smu_7_1_1_d.h"
#include "smu/smu_7_1_1_sh_mask.h"
#include "cgs_common.h"
#include "iceland_smc.h"
#define ICELAND_SMC_SIZE 0x20000
@ -199,7 +200,15 @@ static int iceland_start_smu(struct pp_smumgr *smumgr)
*/
static int iceland_smu_init(struct pp_smumgr *smumgr)
{
return smu7_init(smumgr);
int i;
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
if (smu7_init(smumgr))
return -EINVAL;
for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
smu_data->activity_target[i] = 30;
return 0;
}
static const struct pp_smumgr_func iceland_smu_funcs = {
@ -213,6 +222,16 @@ static const struct pp_smumgr_func iceland_smu_funcs = {
.send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
.download_pptable_settings = NULL,
.upload_pptable_settings = NULL,
.get_offsetof = iceland_get_offsetof,
.process_firmware_header = iceland_process_firmware_header,
.init_smc_table = iceland_init_smc_table,
.update_sclk_threshold = iceland_update_sclk_threshold,
.thermal_setup_fan_table = iceland_thermal_setup_fan_table,
.populate_all_graphic_levels = iceland_populate_all_graphic_levels,
.populate_all_memory_levels = iceland_populate_all_memory_levels,
.get_mac_definition = iceland_get_mac_definition,
.initialize_mc_reg_table = iceland_initialize_mc_reg_table,
.is_dpm_running = iceland_is_dpm_running,
};
int iceland_smum_init(struct pp_smumgr *smumgr)

34
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
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@ -28,10 +28,44 @@
#include "smu7_smumgr.h"
#include "pp_endian.h"
#include "smu71_discrete.h"
struct iceland_pt_defaults {
uint8_t svi_load_line_en;
uint8_t svi_load_line_vddc;
uint8_t tdc_vddc_throttle_release_limit_perc;
uint8_t tdc_mawt;
uint8_t tdc_waterfall_ctl;
uint8_t dte_ambient_temp_base;
uint32_t display_cac;
uint32_t bamp_temp_gradient;
uint16_t bapmti_r[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
uint16_t bapmti_rc[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
};
struct iceland_mc_reg_entry {
uint32_t mclk_max;
uint32_t mc_data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
struct iceland_mc_reg_table {
uint8_t last; /* number of registers*/
uint8_t num_entries; /* number of entries in mc_reg_table_entry used*/
uint16_t validflag; /* indicate the corresponding register is valid or not. 1: valid, 0: invalid. bit0->address[0], bit1->address[1], etc.*/
struct iceland_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
SMU71_Discrete_MCRegisterAddress mc_reg_address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
struct iceland_smumgr {
struct smu7_smumgr smu7_data;
struct SMU71_Discrete_DpmTable smc_state_table;
struct SMU71_Discrete_PmFuses power_tune_table;
struct SMU71_Discrete_Ulv ulv_setting;
struct iceland_pt_defaults *power_tune_defaults;
SMU71_Discrete_MCRegisters mc_regs;
struct iceland_mc_reg_table mc_reg_table;
uint32_t activity_target[SMU71_MAX_LEVELS_GRAPHICS];
};
#endif