[POWERPC] 4xx: Rework clock probing in boot wrapper
This reworks the boot wrapper library function that probes the chip clocks. Better separate the base function that is used on 440GX,SPe,EP,... from the uart fixups as those need different device-tree path on different processors. Also, rework the function itself based on the arch/ppc code from Eugene Surovegin which I find more readable, and which handles one more bypass case. Also handle the subtle difference between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived from the PLB clock while on the later, it's derived from the OPB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>hifive-unleashed-5.1
Benjamin Herrenschmidt
Josh Boyer
parent
bc0b4e7ffb
commit
190de00538
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@ -275,89 +275,225 @@ void ibm4xx_fixup_ebc_ranges(const char *ebc)
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setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
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}
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#define SPRN_CCR1 0x378
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void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
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/* Calculate 440GP clocks */
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void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
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{
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u32 cpu, plb, opb, ebc, tb, uart0, m, vco;
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u32 reg;
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u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp;
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u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
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u32 cr0 = mfdcr(DCRN_CPC0_CR0);
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u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
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u32 opdv = CPC0_SYS0_OPDV(sys0);
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u32 epdv = CPC0_SYS0_EPDV(sys0);
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mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x000F0000) >> 16;
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fwdva = tmp ? tmp : 16;
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tmp = (reg & 0x00000700) >> 8;
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fwdvb = tmp ? tmp : 8;
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tmp = (reg & 0x1F000000) >> 24;
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fbdv = tmp ? tmp : 32;
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lfbdv = (reg & 0x0000007F);
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mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x03000000) >> 24;
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opbdv0 = tmp ? tmp : 4;
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mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x07000000) >> 24;
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perdv0 = tmp ? tmp : 8;
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mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x07000000) >> 24;
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prbdv0 = tmp ? tmp : 8;
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mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x03000000) >> 24;
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spcid0 = tmp ? tmp : 4;
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/* Calculate M */
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mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x03000000) >> 24;
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if (tmp == 0) { /* PLL output */
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tmp = (reg & 0x20000000) >> 29;
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if (!tmp) /* PLLOUTA */
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m = fbdv * lfbdv * fwdva;
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if (sys0 & CPC0_SYS0_BYPASS) {
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/* Bypass system PLL */
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cpu = plb = sys_clk;
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} else {
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if (sys0 & CPC0_SYS0_EXTSL)
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/* PerClk */
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m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
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else
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m = fbdv * lfbdv * fwdvb;
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/* CPU clock */
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m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
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cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0);
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plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0);
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}
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else if (tmp == 1) /* CPU output */
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m = fbdv * fwdva;
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opb = plb / opdv;
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ebc = opb / epdv;
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/* FIXME: Check if this is for all 440GP, or just Ebony */
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if ((mfpvr() & 0xf0000fff) == 0x40000440)
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/* Rev. B 440GP, use external system clock */
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tb = sys_clk;
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else
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m = perdv0 * opbdv0 * fwdvb;
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/* Rev. C 440GP, errata force us to use internal clock */
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tb = cpu;
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vco = (m * sysclk) + (m >> 1);
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cpu = vco / fwdva;
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plb = vco / fwdvb / prbdv0;
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if (cr0 & CPC0_CR0_U0EC)
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/* External UART clock */
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uart0 = ser_clk;
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else
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/* Internal UART clock */
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uart0 = plb / CPC0_CR0_UDIV(cr0);
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if (cr0 & CPC0_CR0_U1EC)
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/* External UART clock */
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uart1 = ser_clk;
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else
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/* Internal UART clock */
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uart1 = plb / CPC0_CR0_UDIV(cr0);
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printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
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(sys_clk + 500000) / 1000000, sys_clk);
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dt_fixup_cpu_clocks(cpu, tb, 0);
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dt_fixup_clock("/plb", plb);
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dt_fixup_clock("/plb/opb", opb);
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dt_fixup_clock("/plb/opb/ebc", ebc);
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dt_fixup_clock("/plb/opb/serial@40000200", uart0);
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dt_fixup_clock("/plb/opb/serial@40000300", uart1);
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}
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#define SPRN_CCR1 0x378
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static inline u32 __fix_zero(u32 v, u32 def)
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{
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return v ? v : def;
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}
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static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk,
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unsigned int tmr_clk,
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int per_clk_from_opb)
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{
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/* PLL config */
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u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
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u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
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/* Dividers */
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u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
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u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16);
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u32 fwdvb = __fix_zero((plld >> 8) & 7, 8);
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u32 lfbdv = __fix_zero(plld & 0x3f, 64);
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u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8);
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u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8);
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u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4);
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u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4);
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/* Input clocks for primary dividers */
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u32 clk_a, clk_b;
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/* Resulting clocks */
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u32 cpu, plb, opb, ebc, vco;
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/* Timebase */
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u32 ccr1, tb = tmr_clk;
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if (pllc & 0x40000000) {
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u32 m;
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/* Feedback path */
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switch ((pllc >> 24) & 7) {
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case 0:
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/* PLLOUTx */
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m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
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break;
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case 1:
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/* CPU */
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m = fwdva * pradv0;
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break;
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case 5:
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/* PERClk */
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m = fwdvb * prbdv0 * opbdv0 * perdv0;
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break;
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default:
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printf("WARNING ! Invalid PLL feedback source !\n");
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goto bypass;
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}
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m *= fbdv;
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vco = sys_clk * m;
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clk_a = vco / fwdva;
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clk_b = vco / fwdvb;
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} else {
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bypass:
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/* Bypass system PLL */
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vco = 0;
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clk_a = clk_b = sys_clk;
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}
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cpu = clk_a / pradv0;
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plb = clk_b / prbdv0;
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opb = plb / opbdv0;
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ebc = plb / perdv0;
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/* FIXME */
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uart0 = ser_clk;
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ebc = (per_clk_from_opb ? opb : plb) / perdv0;
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/* Figure out timebase. Either CPU or default TmrClk */
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asm volatile (
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"mfspr %0,%1\n"
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:
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"=&r"(reg) : "i"(SPRN_CCR1));
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if (reg & 0x0080)
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tb = 25000000; /* TmrClk is 25MHz */
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else
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ccr1 = mfspr(SPRN_CCR1);
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/* If passed a 0 tmr_clk, force CPU clock */
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if (tb == 0) {
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ccr1 &= ~0x80u;
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mtspr(SPRN_CCR1, ccr1);
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}
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if ((ccr1 & 0x0080) == 0)
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tb = cpu;
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dt_fixup_cpu_clocks(cpu, tb, 0);
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dt_fixup_clock("/plb", plb);
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dt_fixup_clock("/plb/opb", opb);
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dt_fixup_clock("/plb/opb/ebc", ebc);
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dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
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dt_fixup_clock("/plb/opb/serial@ef600400", uart0);
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dt_fixup_clock("/plb/opb/serial@ef600500", uart0);
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dt_fixup_clock("/plb/opb/serial@ef600600", uart0);
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return plb;
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}
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void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
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static void eplike_fixup_uart_clk(int index, const char *path,
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unsigned int ser_clk,
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unsigned int plb_clk)
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{
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unsigned int sdr;
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unsigned int clock;
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switch (index) {
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case 0:
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sdr = SDR0_READ(DCRN_SDR0_UART0);
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break;
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case 1:
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sdr = SDR0_READ(DCRN_SDR0_UART1);
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break;
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case 2:
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sdr = SDR0_READ(DCRN_SDR0_UART2);
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break;
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case 3:
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sdr = SDR0_READ(DCRN_SDR0_UART3);
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break;
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default:
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return;
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}
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if (sdr & 0x00800000u)
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clock = ser_clk;
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else
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clock = plb_clk / __fix_zero(sdr & 0xff, 256);
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dt_fixup_clock(path, clock);
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}
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void ibm440ep_fixup_clocks(unsigned int sys_clk,
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unsigned int ser_clk,
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unsigned int tmr_clk)
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{
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unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
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/* serial clocks beed fixup based on int/ext */
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eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
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eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
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eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
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eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk);
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}
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void ibm440gx_fixup_clocks(unsigned int sys_clk,
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unsigned int ser_clk,
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unsigned int tmr_clk)
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{
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unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
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/* serial clocks beed fixup based on int/ext */
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eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
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eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
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}
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void ibm440spe_fixup_clocks(unsigned int sys_clk,
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unsigned int ser_clk,
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unsigned int tmr_clk)
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{
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unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
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/* serial clocks beed fixup based on int/ext */
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eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk);
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eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk);
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eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk);
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}
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void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
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{
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u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
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u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
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@ -374,7 +510,7 @@ void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
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m = fwdv * fbdv * cbdv;
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cpu = sysclk * m / fwdv;
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cpu = sys_clk * m / fwdv;
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plb = cpu / cbdv;
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opb = plb / opdv;
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ebc = plb / epdv;
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@ -18,7 +18,14 @@ void ibm44x_dbcr_reset(void);
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void ibm40x_dbcr_reset(void);
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void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
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void ibm4xx_fixup_ebc_ranges(const char *ebc);
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void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk);
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void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk);
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void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
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void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
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void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
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unsigned int tmr_clk);
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void ibm440gx_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
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unsigned int tmr_clk);
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void ibm440spe_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
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unsigned int tmr_clk);
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#endif /* _POWERPC_BOOT_4XX_H_ */
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@ -30,7 +30,7 @@ static void bamboo_fixups(void)
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{
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unsigned long sysclk = 33333333;
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ibm440ep_fixup_clocks(sysclk, 11059200);
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ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
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ibm4xx_sdram_fixup_memsize();
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ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
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dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
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@ -39,7 +39,7 @@ static void sequoia_fixups(void)
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{
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unsigned long sysclk = 33333333;
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ibm440ep_fixup_clocks(sysclk, 11059200);
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ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
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ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
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ibm4xx_denali_fixup_memsize();
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dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
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@ -34,9 +34,7 @@ static void taishan_fixups(void)
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registers */
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unsigned long sysclk = 33000000;
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/* 440EP Clock logic is all but identical to 440GX
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so we just use that code for now at least */
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ibm440ep_fixup_clocks(sysclk, 6 * 1843200);
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ibm440gx_fixup_clocks(sysclk, 6 * 1843200, 25000000);
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ibm4xx_sdram_fixup_memsize();
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@ -160,6 +160,23 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
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#define DCRN_CPR0_PERD 0x0e0
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#define DCRN_CPR0_MALD 0x100
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#define DCRN_SDR0_CONFIG_ADDR 0xe
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#define DCRN_SDR0_CONFIG_DATA 0xf
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/* SDR read/write helper macros */
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#define SDR0_READ(offset) ({\
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mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
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mfdcr(DCRN_SDR0_CONFIG_DATA); })
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#define SDR0_WRITE(offset, data) ({\
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mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
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mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
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#define DCRN_SDR0_UART0 0x0120
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#define DCRN_SDR0_UART1 0x0121
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#define DCRN_SDR0_UART2 0x0122
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#define DCRN_SDR0_UART3 0x0123
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/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
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#define DCRN_CPR0_CFGADDR 0xc
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@ -31,66 +31,6 @@
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static u8 *ebony_mac0, *ebony_mac1;
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/* Calculate 440GP clocks */
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void ibm440gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
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{
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u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
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u32 cr0 = mfdcr(DCRN_CPC0_CR0);
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u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
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u32 opdv = CPC0_SYS0_OPDV(sys0);
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u32 epdv = CPC0_SYS0_EPDV(sys0);
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if (sys0 & CPC0_SYS0_BYPASS) {
|
||||
/* Bypass system PLL */
|
||||
cpu = plb = sysclk;
|
||||
} else {
|
||||
if (sys0 & CPC0_SYS0_EXTSL)
|
||||
/* PerClk */
|
||||
m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
|
||||
else
|
||||
/* CPU clock */
|
||||
m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
|
||||
cpu = sysclk * m / CPC0_SYS0_FWDVA(sys0);
|
||||
plb = sysclk * m / CPC0_SYS0_FWDVB(sys0);
|
||||
}
|
||||
|
||||
opb = plb / opdv;
|
||||
ebc = opb / epdv;
|
||||
|
||||
/* FIXME: Check if this is for all 440GP, or just Ebony */
|
||||
if ((mfpvr() & 0xf0000fff) == 0x40000440)
|
||||
/* Rev. B 440GP, use external system clock */
|
||||
tb = sysclk;
|
||||
else
|
||||
/* Rev. C 440GP, errata force us to use internal clock */
|
||||
tb = cpu;
|
||||
|
||||
if (cr0 & CPC0_CR0_U0EC)
|
||||
/* External UART clock */
|
||||
uart0 = ser_clk;
|
||||
else
|
||||
/* Internal UART clock */
|
||||
uart0 = plb / CPC0_CR0_UDIV(cr0);
|
||||
|
||||
if (cr0 & CPC0_CR0_U1EC)
|
||||
/* External UART clock */
|
||||
uart1 = ser_clk;
|
||||
else
|
||||
/* Internal UART clock */
|
||||
uart1 = plb / CPC0_CR0_UDIV(cr0);
|
||||
|
||||
printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
|
||||
(sysclk + 500000) / 1000000, sysclk);
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/opb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@40000200", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@40000300", uart1);
|
||||
}
|
||||
|
||||
#define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
|
||||
#define EBONY_FPGA_FLASH_SEL 0x01
|
||||
#define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
|
||||
|
|
|
|||
Loading…
Reference in New Issue