drm/amdgpu: add enumerate for PDB/PTB v3
v2: remove SUBPTB member v3: remove last_level, use AMDGPU_VM_PTB directly instead. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>hifive-unleashed-5.1
Chunming Zhou
Alex Deucher
parent
a53d45d8e4
commit
196f74897b
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@ -148,12 +148,23 @@ struct amdgpu_prt_cb {
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static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
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unsigned level)
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{
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if (level != adev->vm_manager.num_level)
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return 9 * (adev->vm_manager.num_level - level - 1) +
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unsigned shift = 0xff;
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switch (level) {
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case AMDGPU_VM_PDB2:
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case AMDGPU_VM_PDB1:
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case AMDGPU_VM_PDB0:
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shift = 9 * (AMDGPU_VM_PDB0 - level) +
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adev->vm_manager.block_size;
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else
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/* For the page tables on the leaves */
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return 0;
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break;
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case AMDGPU_VM_PTB:
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shift = 0;
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break;
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default:
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dev_err(adev->dev, "the level%d isn't supported.\n", level);
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}
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return shift;
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}
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/**
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@ -166,12 +177,13 @@ static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
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static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
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unsigned level)
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{
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unsigned shift = amdgpu_vm_level_shift(adev, 0);
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unsigned shift = amdgpu_vm_level_shift(adev,
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adev->vm_manager.root_level);
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if (level == 0)
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if (level == adev->vm_manager.root_level)
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/* For the root directory */
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return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift;
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else if (level != adev->vm_manager.num_level)
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else if (level != AMDGPU_VM_PTB)
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/* Everything in between */
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return 512;
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else
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@ -343,7 +355,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
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if (vm->pte_support_ats) {
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init_value = AMDGPU_PTE_DEFAULT_ATC;
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if (level != adev->vm_manager.num_level)
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if (level != AMDGPU_VM_PTB)
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init_value |= AMDGPU_PDE_PTE;
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}
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@ -385,7 +397,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
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spin_unlock(&vm->status_lock);
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}
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if (level < adev->vm_manager.num_level) {
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if (level < AMDGPU_VM_PTB) {
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uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
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uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
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((1 << shift) - 1);
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@ -431,7 +443,8 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
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saddr /= AMDGPU_GPU_PAGE_SIZE;
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eaddr /= AMDGPU_GPU_PAGE_SIZE;
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return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0);
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return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr,
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adev->vm_manager.root_level);
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}
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/**
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@ -1091,6 +1104,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
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for (level = 0, pbo = parent->base.bo->parent; pbo; ++level)
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pbo = pbo->parent;
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level += params->adev->vm_manager.root_level;
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pt = amdgpu_bo_gpu_offset(bo);
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flags = AMDGPU_PTE_VALID;
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amdgpu_gart_get_vm_pde(params->adev, level, &pt, &flags);
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@ -1247,7 +1261,8 @@ restart:
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return 0;
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error:
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amdgpu_vm_invalidate_level(adev, vm, &vm->root, 0);
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amdgpu_vm_invalidate_level(adev, vm, &vm->root,
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adev->vm_manager.root_level);
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amdgpu_job_free(job);
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return r;
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}
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@ -1266,7 +1281,7 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
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struct amdgpu_vm_pt **entry,
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struct amdgpu_vm_pt **parent)
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{
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unsigned level = 0;
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unsigned level = p->adev->vm_manager.root_level;
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*parent = NULL;
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*entry = &p->vm->root;
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@ -1278,7 +1293,7 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
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addr &= (1ULL << shift) - 1;
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}
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if (level != p->adev->vm_manager.num_level)
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if (level != AMDGPU_VM_PTB)
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*entry = NULL;
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}
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@ -1320,7 +1335,7 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
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return;
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entry->huge = !!(flags & AMDGPU_PDE_PTE);
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amdgpu_gart_get_vm_pde(p->adev, p->adev->vm_manager.num_level - 1,
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amdgpu_gart_get_vm_pde(p->adev, AMDGPU_VM_PDB0,
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&dst, &flags);
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if (use_cpu_update) {
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@ -1636,7 +1651,8 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
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error_free:
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amdgpu_job_free(job);
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amdgpu_vm_invalidate_level(adev, vm, &vm->root, 0);
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amdgpu_vm_invalidate_level(adev, vm, &vm->root,
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adev->vm_manager.root_level);
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return r;
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}
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@ -2552,7 +2568,19 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
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tmp >>= amdgpu_vm_block_size - 9;
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tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
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adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
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switch (adev->vm_manager.num_level) {
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case 3:
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adev->vm_manager.root_level = AMDGPU_VM_PDB2;
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break;
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case 2:
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adev->vm_manager.root_level = AMDGPU_VM_PDB1;
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break;
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case 1:
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adev->vm_manager.root_level = AMDGPU_VM_PDB0;
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break;
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default:
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dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
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}
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/* block size depends on vm size and hw setup*/
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if (amdgpu_vm_block_size != -1)
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adev->vm_manager.block_size =
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@ -2646,7 +2674,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
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AMDGPU_GEM_CREATE_SHADOW);
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r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
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r = amdgpu_bo_create(adev,
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amdgpu_vm_bo_size(adev, adev->vm_manager.root_level),
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align, true,
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AMDGPU_GEM_DOMAIN_VRAM,
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flags,
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NULL, NULL, init_pde_value, &vm->root.base.bo);
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@ -2782,7 +2812,8 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
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if (r) {
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dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
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} else {
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amdgpu_vm_free_levels(adev, &vm->root, 0);
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amdgpu_vm_free_levels(adev, &vm->root,
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adev->vm_manager.root_level);
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amdgpu_bo_unreserve(root);
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}
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amdgpu_bo_unref(&root);
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@ -120,6 +120,16 @@ struct amdgpu_bo_list_entry;
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#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
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#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
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/* VMPT level enumerate, and the hiberachy is:
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* PDB2->PDB1->PDB0->PTB
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*/
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enum amdgpu_vm_level {
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AMDGPU_VM_PDB2,
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AMDGPU_VM_PDB1,
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AMDGPU_VM_PDB0,
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AMDGPU_VM_PTB
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};
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/* base structure for tracking BO usage in a VM */
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struct amdgpu_vm_bo_base {
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/* constant after initialization */
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@ -236,6 +246,7 @@ struct amdgpu_vm_manager {
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uint32_t num_level;
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uint32_t block_size;
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uint32_t fragment_size;
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enum amdgpu_vm_level root_level;
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/* vram base address for page table entry */
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u64 vram_base_offset;
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/* vm pte handling */
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