soc/tegra: pmc: Add wake event support
The power management controller has top-level controls that allow certain interrupts (such as from the RTC or a subset of GPIOs) to wake the system from sleep. Implement infrastructure to support these wake events. Signed-off-by: Thierry Reding <treding@nvidia.com>hifive-unleashed-5.1
Thierry Reding
parent
eac9c48aac
commit
19906e6b16
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@ -30,9 +30,12 @@
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_clk.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf.h>
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@ -49,6 +52,7 @@
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/pmc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
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#define PMC_CNTRL 0x0
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@ -126,6 +130,16 @@
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#define GPU_RG_CNTRL 0x2d4
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/* Tegra186 and later */
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#define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
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#define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
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#define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
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#define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
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#define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
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#define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
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#define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
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#define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
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#define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
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#define WAKE_AOWAKE_CTRL 0x4f4
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#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
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@ -158,6 +172,38 @@ struct tegra_pmc_regs {
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unsigned int rst_level_mask;
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};
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struct tegra_wake_event {
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const char *name;
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unsigned int id;
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unsigned int irq;
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struct {
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unsigned int instance;
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unsigned int pin;
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} gpio;
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};
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#define TEGRA_WAKE_IRQ(_name, _id, _irq) \
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{ \
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.name = _name, \
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.id = _id, \
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.irq = _irq, \
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.gpio = { \
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.instance = UINT_MAX, \
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.pin = UINT_MAX, \
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}, \
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}
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#define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
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{ \
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.name = _name, \
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.id = _id, \
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.irq = 0, \
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.gpio = { \
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.instance = _instance, \
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.pin = _pin, \
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}, \
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}
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struct tegra_pmc_soc {
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unsigned int num_powergates;
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const char *const *powergates;
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@ -185,6 +231,9 @@ struct tegra_pmc_soc {
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unsigned int num_reset_sources;
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const char * const *reset_levels;
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unsigned int num_reset_levels;
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const struct tegra_wake_event *wake_events;
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unsigned int num_wake_events;
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};
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static const char * const tegra186_reset_sources[] = {
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@ -271,6 +320,9 @@ struct tegra_pmc {
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struct mutex powergates_lock;
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struct pinctrl_dev *pctl_dev;
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struct irq_domain *domain;
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struct irq_chip irq;
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};
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static struct tegra_pmc *pmc = &(struct tegra_pmc) {
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@ -1602,6 +1654,175 @@ static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
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}
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}
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static int tegra_pmc_irq_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (WARN_ON(fwspec->param_count < 2))
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return -EINVAL;
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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return 0;
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}
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static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int num_irqs, void *data)
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{
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struct tegra_pmc *pmc = domain->host_data;
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const struct tegra_pmc_soc *soc = pmc->soc;
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struct irq_fwspec *fwspec = data;
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unsigned int i;
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int err = 0;
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for (i = 0; i < soc->num_wake_events; i++) {
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const struct tegra_wake_event *event = &soc->wake_events[i];
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if (fwspec->param_count == 2) {
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struct irq_fwspec spec;
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if (event->id != fwspec->param[0])
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continue;
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err = irq_domain_set_hwirq_and_chip(domain, virq,
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event->id,
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&pmc->irq, pmc);
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if (err < 0)
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break;
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spec.fwnode = &pmc->dev->of_node->fwnode;
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spec.param_count = 3;
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spec.param[0] = GIC_SPI;
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spec.param[1] = event->irq;
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spec.param[2] = fwspec->param[1];
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err = irq_domain_alloc_irqs_parent(domain, virq,
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num_irqs, &spec);
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break;
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}
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if (fwspec->param_count == 3) {
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if (event->gpio.instance != fwspec->param[0] ||
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event->gpio.pin != fwspec->param[1])
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continue;
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err = irq_domain_set_hwirq_and_chip(domain, virq,
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event->id,
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&pmc->irq, pmc);
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break;
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}
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}
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if (i == soc->num_wake_events)
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err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX,
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&pmc->irq, pmc);
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return err;
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}
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static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
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.translate = tegra_pmc_irq_translate,
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.alloc = tegra_pmc_irq_alloc,
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};
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static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
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unsigned int offset, bit;
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u32 value;
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offset = data->hwirq / 32;
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bit = data->hwirq % 32;
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/* clear wake status */
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writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
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/* route wake to tier 2 */
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value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
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if (!on)
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value &= ~(1 << bit);
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else
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value |= 1 << bit;
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writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
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/* enable wakeup event */
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writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
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return 0;
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}
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static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
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u32 value;
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if (data->hwirq == ULONG_MAX)
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return 0;
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value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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value |= WAKE_AOWAKE_CNTRL_LEVEL;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
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break;
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case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
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value ^= WAKE_AOWAKE_CNTRL_LEVEL;
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break;
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default:
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return -EINVAL;
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}
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writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
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return 0;
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}
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static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
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{
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struct irq_domain *parent = NULL;
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struct device_node *np;
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np = of_irq_find_parent(pmc->dev->of_node);
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if (np) {
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parent = irq_find_host(np);
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of_node_put(np);
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}
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if (!parent)
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return 0;
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pmc->irq.name = dev_name(pmc->dev);
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pmc->irq.irq_mask = irq_chip_mask_parent;
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pmc->irq.irq_unmask = irq_chip_unmask_parent;
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pmc->irq.irq_eoi = irq_chip_eoi_parent;
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pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent;
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pmc->irq.irq_set_type = tegra_pmc_irq_set_type;
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pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake;
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pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
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&tegra_pmc_irq_domain_ops, pmc);
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if (!pmc->domain) {
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dev_err(pmc->dev, "failed to allocate domain\n");
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return -ENOMEM;
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}
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return 0;
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}
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static int tegra_pmc_probe(struct platform_device *pdev)
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{
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void __iomem *base;
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@ -1690,6 +1911,10 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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if (err)
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goto cleanup_restart_handler;
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err = tegra_pmc_irq_init(pmc);
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if (err < 0)
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goto cleanup_restart_handler;
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mutex_lock(&pmc->powergates_lock);
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iounmap(pmc->base);
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pmc->base = base;
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