pinctrl: intel: Add Intel Cannon Lake PCH pin controller support
This adds pinctrl/GPIO support for Intel Cannon Lake PCH. The Cannon Lake PCH GPIO is based on newer version of the Intel GPIO hardware. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>hifive-unleashed-5.1
Mika Westerberg
Linus Walleij
parent
1f6b419b24
commit
19a8a77717
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@ -56,6 +56,14 @@ config PINCTRL_BROXTON
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Broxton pinctrl driver provides an interface that allows
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Broxton pinctrl driver provides an interface that allows
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configuring of SoC pins and using them as GPIOs.
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configuring of SoC pins and using them as GPIOs.
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config PINCTRL_CANNONLAKE
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tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
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depends on ACPI
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select PINCTRL_INTEL
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help
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This pinctrl driver provides an interface that allows configuring
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of Intel Cannon Lake PCH pins and using them as GPIOs.
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config PINCTRL_GEMINILAKE
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config PINCTRL_GEMINILAKE
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tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
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tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
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depends on ACPI
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depends on ACPI
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@ -5,5 +5,6 @@ obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
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obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
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obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
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obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
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obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
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obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
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obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
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obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
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obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
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obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
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obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
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obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
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@ -0,0 +1,442 @@
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/*
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* Intel Cannon Lake PCH pinctrl/GPIO driver
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*
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* Copyright (C) 2017, Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/acpi.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-intel.h"
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#define CNL_PAD_OWN 0x020
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#define CNL_PADCFGLOCK 0x080
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#define CNL_HOSTSW_OWN 0x0b0
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#define CNL_GPI_IE 0x120
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#define CNL_GPP(r, s, e) \
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{ \
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.reg_num = (r), \
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.base = (s), \
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.size = ((e) - (s) + 1), \
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}
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#define CNL_COMMUNITY(b, s, e, g) \
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{ \
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.barno = (b), \
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.padown_offset = CNL_PAD_OWN, \
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.padcfglock_offset = CNL_PADCFGLOCK, \
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.hostown_offset = CNL_HOSTSW_OWN, \
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.ie_offset = CNL_GPI_IE, \
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.pin_base = (s), \
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.npins = ((e) - (s) + 1), \
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.gpps = (g), \
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.ngpps = ARRAY_SIZE(g), \
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}
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/* Cannon Lake-LP */
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static const struct pinctrl_pin_desc cnllp_pins[] = {
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/* GPP_A */
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PINCTRL_PIN(0, "RCINB"),
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PINCTRL_PIN(1, "LAD_0"),
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PINCTRL_PIN(2, "LAD_1"),
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PINCTRL_PIN(3, "LAD_2"),
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PINCTRL_PIN(4, "LAD_3"),
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PINCTRL_PIN(5, "LFRAMEB"),
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PINCTRL_PIN(6, "SERIRQ"),
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PINCTRL_PIN(7, "PIRQAB"),
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PINCTRL_PIN(8, "CLKRUNB"),
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PINCTRL_PIN(9, "CLKOUT_LPC_0"),
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PINCTRL_PIN(10, "CLKOUT_LPC_1"),
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PINCTRL_PIN(11, "PMEB"),
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PINCTRL_PIN(12, "BM_BUSYB"),
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PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
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PINCTRL_PIN(14, "SUS_STATB"),
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PINCTRL_PIN(15, "SUSACKB"),
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PINCTRL_PIN(16, "SD_1P8_SEL"),
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PINCTRL_PIN(17, "SD_PWR_EN_B"),
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PINCTRL_PIN(18, "ISH_GP_0"),
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PINCTRL_PIN(19, "ISH_GP_1"),
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PINCTRL_PIN(20, "ISH_GP_2"),
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PINCTRL_PIN(21, "ISH_GP_3"),
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PINCTRL_PIN(22, "ISH_GP_4"),
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PINCTRL_PIN(23, "ISH_GP_5"),
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PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
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/* GPP_B */
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PINCTRL_PIN(25, "CORE_VID_0"),
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PINCTRL_PIN(26, "CORE_VID_1"),
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PINCTRL_PIN(27, "VRALERTB"),
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PINCTRL_PIN(28, "CPU_GP_2"),
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PINCTRL_PIN(29, "CPU_GP_3"),
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PINCTRL_PIN(30, "SRCCLKREQB_0"),
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PINCTRL_PIN(31, "SRCCLKREQB_1"),
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PINCTRL_PIN(32, "SRCCLKREQB_2"),
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PINCTRL_PIN(33, "SRCCLKREQB_3"),
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PINCTRL_PIN(34, "SRCCLKREQB_4"),
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PINCTRL_PIN(35, "SRCCLKREQB_5"),
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PINCTRL_PIN(36, "EXT_PWR_GATEB"),
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PINCTRL_PIN(37, "SLP_S0B"),
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PINCTRL_PIN(38, "PLTRSTB"),
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PINCTRL_PIN(39, "SPKR"),
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PINCTRL_PIN(40, "GSPI0_CS0B"),
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PINCTRL_PIN(41, "GSPI0_CLK"),
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PINCTRL_PIN(42, "GSPI0_MISO"),
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PINCTRL_PIN(43, "GSPI0_MOSI"),
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PINCTRL_PIN(44, "GSPI1_CS0B"),
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PINCTRL_PIN(45, "GSPI1_CLK"),
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PINCTRL_PIN(46, "GSPI1_MISO"),
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PINCTRL_PIN(47, "GSPI1_MOSI"),
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PINCTRL_PIN(48, "SML1ALERTB"),
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PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
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PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
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/* GPP_G */
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PINCTRL_PIN(51, "SD3_CMD"),
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PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"),
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PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"),
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PINCTRL_PIN(54, "SD3_D2"),
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PINCTRL_PIN(55, "SD3_D3"),
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PINCTRL_PIN(56, "SD3_CDB"),
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PINCTRL_PIN(57, "SD3_CLK"),
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PINCTRL_PIN(58, "SD3_WP"),
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/* SPI */
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PINCTRL_PIN(59, "SPI0_IO_2"),
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PINCTRL_PIN(60, "SPI0_IO_3"),
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PINCTRL_PIN(61, "SPI0_MOSI_IO_0"),
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PINCTRL_PIN(62, "SPI0_MISO_IO_1"),
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PINCTRL_PIN(63, "SPI0_TPM_CSB"),
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PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"),
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PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"),
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PINCTRL_PIN(66, "SPI0_CLK"),
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PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"),
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/* GPP_D */
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PINCTRL_PIN(68, "SPI1_CSB"),
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PINCTRL_PIN(69, "SPI1_CLK"),
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PINCTRL_PIN(70, "SPI1_MISO_IO_1"),
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PINCTRL_PIN(71, "SPI1_MOSI_IO_0"),
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PINCTRL_PIN(72, "IMGCLKOUT_0"),
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PINCTRL_PIN(73, "ISH_I2C0_SDA"),
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PINCTRL_PIN(74, "ISH_I2C0_SCL"),
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PINCTRL_PIN(75, "ISH_I2C1_SDA"),
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PINCTRL_PIN(76, "ISH_I2C1_SCL"),
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PINCTRL_PIN(77, "ISH_SPI_CSB"),
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PINCTRL_PIN(78, "ISH_SPI_CLK"),
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PINCTRL_PIN(79, "ISH_SPI_MISO"),
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PINCTRL_PIN(80, "ISH_SPI_MOSI"),
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PINCTRL_PIN(81, "ISH_UART0_RXD"),
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PINCTRL_PIN(82, "ISH_UART0_TXD"),
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PINCTRL_PIN(83, "ISH_UART0_RTSB"),
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PINCTRL_PIN(84, "ISH_UART0_CTSB"),
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PINCTRL_PIN(85, "DMIC_CLK_1"),
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PINCTRL_PIN(86, "DMIC_DATA_1"),
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PINCTRL_PIN(87, "DMIC_CLK_0"),
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PINCTRL_PIN(88, "DMIC_DATA_0"),
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PINCTRL_PIN(89, "SPI1_IO_2"),
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PINCTRL_PIN(90, "SPI1_IO_3"),
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PINCTRL_PIN(91, "SSP_MCLK"),
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PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"),
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/* GPP_F */
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PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"),
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PINCTRL_PIN(94, "CNV_GNSS_FTA"),
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PINCTRL_PIN(95, "CNV_GNSS_SYSCK"),
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PINCTRL_PIN(96, "EMMC_HIP_MON"),
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PINCTRL_PIN(97, "CNV_BRI_DT"),
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PINCTRL_PIN(98, "CNV_BRI_RSP"),
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PINCTRL_PIN(99, "CNV_RGI_DT"),
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PINCTRL_PIN(100, "CNV_RGI_RSP"),
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PINCTRL_PIN(101, "CNV_MFUART2_RXD"),
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PINCTRL_PIN(102, "CNV_MFUART2_TXD"),
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PINCTRL_PIN(103, "GPP_F_10"),
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PINCTRL_PIN(104, "EMMC_CMD"),
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PINCTRL_PIN(105, "EMMC_DATA_0"),
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PINCTRL_PIN(106, "EMMC_DATA_1"),
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PINCTRL_PIN(107, "EMMC_DATA_2"),
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PINCTRL_PIN(108, "EMMC_DATA_3"),
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PINCTRL_PIN(109, "EMMC_DATA_4"),
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PINCTRL_PIN(110, "EMMC_DATA_5"),
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PINCTRL_PIN(111, "EMMC_DATA_6"),
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PINCTRL_PIN(112, "EMMC_DATA_7"),
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PINCTRL_PIN(113, "EMMC_RCLK"),
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PINCTRL_PIN(114, "EMMC_CLK"),
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PINCTRL_PIN(115, "EMMC_RESETB"),
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PINCTRL_PIN(116, "A4WP_PRESENT"),
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/* GPP_H */
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PINCTRL_PIN(117, "SSP2_SCLK"),
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PINCTRL_PIN(118, "SSP2_SFRM"),
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PINCTRL_PIN(119, "SSP2_TXD"),
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PINCTRL_PIN(120, "SSP2_RXD"),
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PINCTRL_PIN(121, "I2C2_SDA"),
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PINCTRL_PIN(122, "I2C2_SCL"),
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PINCTRL_PIN(123, "I2C3_SDA"),
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PINCTRL_PIN(124, "I2C3_SCL"),
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PINCTRL_PIN(125, "I2C4_SDA"),
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PINCTRL_PIN(126, "I2C4_SCL"),
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PINCTRL_PIN(127, "I2C5_SDA"),
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PINCTRL_PIN(128, "I2C5_SCL"),
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PINCTRL_PIN(129, "M2_SKT2_CFG_0"),
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PINCTRL_PIN(130, "M2_SKT2_CFG_1"),
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PINCTRL_PIN(131, "M2_SKT2_CFG_2"),
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PINCTRL_PIN(132, "M2_SKT2_CFG_3"),
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PINCTRL_PIN(133, "DDPF_CTRLCLK"),
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PINCTRL_PIN(134, "DDPF_CTRLDATA"),
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PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"),
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PINCTRL_PIN(136, "TIMESYNC_0"),
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PINCTRL_PIN(137, "IMGCLKOUT_1"),
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PINCTRL_PIN(138, "GPPC_H_21"),
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PINCTRL_PIN(139, "GPPC_H_22"),
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PINCTRL_PIN(140, "GPPC_H_23"),
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/* vGPIO */
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PINCTRL_PIN(141, "CNV_BTEN"),
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PINCTRL_PIN(142, "CNV_GNEN"),
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PINCTRL_PIN(143, "CNV_WFEN"),
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PINCTRL_PIN(144, "CNV_WCEN"),
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PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
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PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
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PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
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PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
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PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
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PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
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PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
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PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
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PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
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PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
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PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"),
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PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"),
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PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"),
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PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"),
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PINCTRL_PIN(159, "vUART0_TXD"),
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PINCTRL_PIN(160, "vUART0_RXD"),
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PINCTRL_PIN(161, "vUART0_CTS_B"),
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PINCTRL_PIN(162, "vUART0_RTS_B"),
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PINCTRL_PIN(163, "vISH_UART0_TXD"),
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PINCTRL_PIN(164, "vISH_UART0_RXD"),
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PINCTRL_PIN(165, "vISH_UART0_CTS_B"),
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PINCTRL_PIN(166, "vISH_UART0_RTS_B"),
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PINCTRL_PIN(167, "vISH_UART1_TXD"),
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PINCTRL_PIN(168, "vISH_UART1_RXD"),
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PINCTRL_PIN(169, "vISH_UART1_CTS_B"),
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PINCTRL_PIN(170, "vISH_UART1_RTS_B"),
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PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"),
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PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"),
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PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"),
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PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"),
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PINCTRL_PIN(175, "vSSP2_SCLK"),
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PINCTRL_PIN(176, "vSSP2_SFRM"),
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PINCTRL_PIN(177, "vSSP2_TXD"),
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PINCTRL_PIN(178, "vSSP2_RXD"),
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PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"),
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PINCTRL_PIN(180, "vSD3_CD_B"),
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/* GPP_C */
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PINCTRL_PIN(181, "SMBCLK"),
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PINCTRL_PIN(182, "SMBDATA"),
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PINCTRL_PIN(183, "SMBALERTB"),
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PINCTRL_PIN(184, "SML0CLK"),
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PINCTRL_PIN(185, "SML0DATA"),
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PINCTRL_PIN(186, "SML0ALERTB"),
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PINCTRL_PIN(187, "SML1CLK"),
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PINCTRL_PIN(188, "SML1DATA"),
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PINCTRL_PIN(189, "UART0_RXD"),
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PINCTRL_PIN(190, "UART0_TXD"),
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PINCTRL_PIN(191, "UART0_RTSB"),
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PINCTRL_PIN(192, "UART0_CTSB"),
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PINCTRL_PIN(193, "UART1_RXD"),
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PINCTRL_PIN(194, "UART1_TXD"),
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PINCTRL_PIN(195, "UART1_RTSB"),
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PINCTRL_PIN(196, "UART1_CTSB"),
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PINCTRL_PIN(197, "I2C0_SDA"),
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PINCTRL_PIN(198, "I2C0_SCL"),
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PINCTRL_PIN(199, "I2C1_SDA"),
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PINCTRL_PIN(200, "I2C1_SCL"),
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PINCTRL_PIN(201, "UART2_RXD"),
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PINCTRL_PIN(202, "UART2_TXD"),
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PINCTRL_PIN(203, "UART2_RTSB"),
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PINCTRL_PIN(204, "UART2_CTSB"),
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/* GPP_E */
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PINCTRL_PIN(205, "SATAXPCIE_0"),
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PINCTRL_PIN(206, "SATAXPCIE_1"),
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||||||
|
PINCTRL_PIN(207, "SATAXPCIE_2"),
|
||||||
|
PINCTRL_PIN(208, "CPU_GP_0"),
|
||||||
|
PINCTRL_PIN(209, "SATA_DEVSLP_0"),
|
||||||
|
PINCTRL_PIN(210, "SATA_DEVSLP_1"),
|
||||||
|
PINCTRL_PIN(211, "SATA_DEVSLP_2"),
|
||||||
|
PINCTRL_PIN(212, "CPU_GP_1"),
|
||||||
|
PINCTRL_PIN(213, "SATA_LEDB"),
|
||||||
|
PINCTRL_PIN(214, "USB2_OCB_0"),
|
||||||
|
PINCTRL_PIN(215, "USB2_OCB_1"),
|
||||||
|
PINCTRL_PIN(216, "USB2_OCB_2"),
|
||||||
|
PINCTRL_PIN(217, "USB2_OCB_3"),
|
||||||
|
PINCTRL_PIN(218, "DDSP_HPD_0"),
|
||||||
|
PINCTRL_PIN(219, "DDSP_HPD_1"),
|
||||||
|
PINCTRL_PIN(220, "DDSP_HPD_2"),
|
||||||
|
PINCTRL_PIN(221, "DDSP_HPD_3"),
|
||||||
|
PINCTRL_PIN(222, "EDP_HPD"),
|
||||||
|
PINCTRL_PIN(223, "DDPB_CTRLCLK"),
|
||||||
|
PINCTRL_PIN(224, "DDPB_CTRLDATA"),
|
||||||
|
PINCTRL_PIN(225, "DDPC_CTRLCLK"),
|
||||||
|
PINCTRL_PIN(226, "DDPC_CTRLDATA"),
|
||||||
|
PINCTRL_PIN(227, "DDPD_CTRLCLK"),
|
||||||
|
PINCTRL_PIN(228, "DDPD_CTRLDATA"),
|
||||||
|
/* JTAG */
|
||||||
|
PINCTRL_PIN(229, "JTAG_TDO"),
|
||||||
|
PINCTRL_PIN(230, "JTAGX"),
|
||||||
|
PINCTRL_PIN(231, "PRDYB"),
|
||||||
|
PINCTRL_PIN(232, "PREQB"),
|
||||||
|
PINCTRL_PIN(233, "CPU_TRSTB"),
|
||||||
|
PINCTRL_PIN(234, "JTAG_TDI"),
|
||||||
|
PINCTRL_PIN(235, "JTAG_TMS"),
|
||||||
|
PINCTRL_PIN(236, "JTAG_TCK"),
|
||||||
|
PINCTRL_PIN(237, "ITP_PMODE"),
|
||||||
|
/* HVCMOS */
|
||||||
|
PINCTRL_PIN(238, "L_BKLTEN"),
|
||||||
|
PINCTRL_PIN(239, "L_BKLTCTL"),
|
||||||
|
PINCTRL_PIN(240, "L_VDDEN"),
|
||||||
|
PINCTRL_PIN(241, "SYS_PWROK"),
|
||||||
|
PINCTRL_PIN(242, "SYS_RESETB"),
|
||||||
|
PINCTRL_PIN(243, "MLK_RSTB"),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 };
|
||||||
|
static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 };
|
||||||
|
static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 };
|
||||||
|
static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 };
|
||||||
|
static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 };
|
||||||
|
static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
|
||||||
|
|
||||||
|
static const unsigned int cnllp_i2c0_pins[] = { 197, 198 };
|
||||||
|
static const unsigned int cnllp_i2c1_pins[] = { 199, 200 };
|
||||||
|
static const unsigned int cnllp_i2c2_pins[] = { 121, 122 };
|
||||||
|
static const unsigned int cnllp_i2c3_pins[] = { 123, 124 };
|
||||||
|
static const unsigned int cnllp_i2c4_pins[] = { 125, 126 };
|
||||||
|
static const unsigned int cnllp_i2c5_pins[] = { 127, 128 };
|
||||||
|
|
||||||
|
static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 };
|
||||||
|
static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 };
|
||||||
|
static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 };
|
||||||
|
|
||||||
|
static const struct intel_pingroup cnllp_groups[] = {
|
||||||
|
PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes),
|
||||||
|
PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes),
|
||||||
|
PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes),
|
||||||
|
PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1),
|
||||||
|
PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1),
|
||||||
|
PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1),
|
||||||
|
PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1),
|
||||||
|
PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1),
|
||||||
|
PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1),
|
||||||
|
PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1),
|
||||||
|
PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1),
|
||||||
|
PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const cnllp_spi0_groups[] = { "spi0_grp" };
|
||||||
|
static const char * const cnllp_spi1_groups[] = { "spi1_grp" };
|
||||||
|
static const char * const cnllp_spi2_groups[] = { "spi2_grp" };
|
||||||
|
static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" };
|
||||||
|
static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" };
|
||||||
|
static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" };
|
||||||
|
static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" };
|
||||||
|
static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" };
|
||||||
|
static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" };
|
||||||
|
static const char * const cnllp_uart0_groups[] = { "uart0_grp" };
|
||||||
|
static const char * const cnllp_uart1_groups[] = { "uart1_grp" };
|
||||||
|
static const char * const cnllp_uart2_groups[] = { "uart2_grp" };
|
||||||
|
|
||||||
|
static const struct intel_function cnllp_functions[] = {
|
||||||
|
FUNCTION("spi0", cnllp_spi0_groups),
|
||||||
|
FUNCTION("spi1", cnllp_spi1_groups),
|
||||||
|
FUNCTION("spi2", cnllp_spi2_groups),
|
||||||
|
FUNCTION("i2c0", cnllp_i2c0_groups),
|
||||||
|
FUNCTION("i2c1", cnllp_i2c1_groups),
|
||||||
|
FUNCTION("i2c2", cnllp_i2c2_groups),
|
||||||
|
FUNCTION("i2c3", cnllp_i2c3_groups),
|
||||||
|
FUNCTION("i2c4", cnllp_i2c4_groups),
|
||||||
|
FUNCTION("i2c5", cnllp_i2c5_groups),
|
||||||
|
FUNCTION("uart0", cnllp_uart0_groups),
|
||||||
|
FUNCTION("uart1", cnllp_uart1_groups),
|
||||||
|
FUNCTION("uart2", cnllp_uart2_groups),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct intel_padgroup cnllp_community0_gpps[] = {
|
||||||
|
CNL_GPP(0, 0, 24), /* GPP_A */
|
||||||
|
CNL_GPP(1, 25, 50), /* GPP_B */
|
||||||
|
CNL_GPP(2, 51, 58), /* GPP_G */
|
||||||
|
CNL_GPP(3, 59, 67), /* SPI */
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct intel_padgroup cnllp_community1_gpps[] = {
|
||||||
|
CNL_GPP(0, 68, 92), /* GPP_D */
|
||||||
|
CNL_GPP(1, 93, 116), /* GPP_F */
|
||||||
|
CNL_GPP(2, 117, 140), /* GPP_H */
|
||||||
|
CNL_GPP(3, 141, 172), /* vGPIO */
|
||||||
|
CNL_GPP(4, 173, 180), /* vGPIO */
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct intel_padgroup cnllp_community4_gpps[] = {
|
||||||
|
CNL_GPP(0, 181, 204), /* GPP_C */
|
||||||
|
CNL_GPP(1, 205, 228), /* GPP_E */
|
||||||
|
CNL_GPP(2, 229, 237), /* JTAG */
|
||||||
|
CNL_GPP(3, 238, 243), /* HVCMOS */
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct intel_community cnllp_communities[] = {
|
||||||
|
CNL_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
|
||||||
|
CNL_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
|
||||||
|
CNL_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct intel_pinctrl_soc_data cnllp_soc_data = {
|
||||||
|
.pins = cnllp_pins,
|
||||||
|
.npins = ARRAY_SIZE(cnllp_pins),
|
||||||
|
.groups = cnllp_groups,
|
||||||
|
.ngroups = ARRAY_SIZE(cnllp_groups),
|
||||||
|
.functions = cnllp_functions,
|
||||||
|
.nfunctions = ARRAY_SIZE(cnllp_functions),
|
||||||
|
.communities = cnllp_communities,
|
||||||
|
.ncommunities = ARRAY_SIZE(cnllp_communities),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
|
||||||
|
{ "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
|
||||||
|
{ },
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
|
||||||
|
|
||||||
|
static int cnl_pinctrl_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
const struct intel_pinctrl_soc_data *soc_data;
|
||||||
|
const struct acpi_device_id *id;
|
||||||
|
|
||||||
|
id = acpi_match_device(cnl_pinctrl_acpi_match, &pdev->dev);
|
||||||
|
if (!id || !id->driver_data)
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
|
soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
|
||||||
|
return intel_pinctrl_probe(pdev, soc_data);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct dev_pm_ops cnl_pinctrl_pm_ops = {
|
||||||
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
|
||||||
|
intel_pinctrl_resume)
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_driver cnl_pinctrl_driver = {
|
||||||
|
.probe = cnl_pinctrl_probe,
|
||||||
|
.driver = {
|
||||||
|
.name = "cannonlake-pinctrl",
|
||||||
|
.acpi_match_table = cnl_pinctrl_acpi_match,
|
||||||
|
.pm = &cnl_pinctrl_pm_ops,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
module_platform_driver(cnl_pinctrl_driver);
|
||||||
|
|
||||||
|
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
|
||||||
|
MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
Loading…
Reference in New Issue