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drm/nv50: use register/unregister functionality for PDISPLAY ISR 

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
hifive-unleashed-5.1
Ben Skeggs 2010-11-03 10:27:27 +10:00
parent 2cbd4c8185
commit 19b7fc7bf5
4 changed files with 13 additions and 18 deletions
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16
drivers/gpu/drm/nouveau/nouveau_irq.c
View File

@ -38,10 +38,6 @@
#include "nouveau_ramht.h"
#include "nouveau_util.h"
/* needed for hotplug irq */
#include "nouveau_connector.h"
#include "nv50_display.h"
void
nouveau_irq_preinstall(struct drm_device *dev)
{
@ -50,12 +46,7 @@ nouveau_irq_preinstall(struct drm_device *dev)
/* Master disable */
nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
if (dev_priv->card_type >= NV_50) {
INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
spin_lock_init(&dev_priv->hpd_state.lock);
INIT_LIST_HEAD(&dev_priv->vbl_waiting);
}
INIT_LIST_HEAD(&dev_priv->vbl_waiting);
}
int
@ -1238,11 +1229,6 @@ nouveau_irq_handler(DRM_IRQ_ARGS)
status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
}
if (status & NV_PMC_INTR_0_NV50_DISPLAY_PENDING) {
nv50_display_irq_handler(dev);
status &= ~NV_PMC_INTR_0_NV50_DISPLAY_PENDING;
}
for (i = 0; i < 32 && status; i++) {
if (!(status & (1 << i)) || !dev_priv->irq_handler[i])
continue;

10
drivers/gpu/drm/nouveau/nv50_display.c
View File

@ -33,6 +33,8 @@
#include "nouveau_ramht.h"
#include "drm_crtc_helper.h"
static void nv50_display_isr(struct drm_device *);
static inline int
nv50_sor_nr(struct drm_device *dev)
{
@ -328,6 +330,9 @@ int nv50_display_create(struct drm_device *dev)
}
}
INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
nouveau_irq_register(dev, 26, nv50_display_isr);
ret = nv50_display_init(dev);
if (ret) {
nv50_display_destroy(dev);
@ -345,6 +350,7 @@ nv50_display_destroy(struct drm_device *dev)
drm_mode_config_cleanup(dev);
nv50_display_disable(dev);
nouveau_irq_unregister(dev, 26);
}
static u16
@ -863,8 +869,8 @@ nv50_display_irq_hotplug_bh(struct work_struct *work)
drm_helper_hpd_irq_event(dev);
}
void
nv50_display_irq_handler(struct drm_device *dev)
static void
nv50_display_isr(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t delayed = 0;

1
drivers/gpu/drm/nouveau/nv50_display.h
View File

@ -35,7 +35,6 @@
#include "nouveau_crtc.h"
#include "nv50_evo.h"
void nv50_display_irq_handler(struct drm_device *dev);
void nv50_display_irq_handler_bh(struct work_struct *work);
void nv50_display_irq_hotplug_bh(struct work_struct *work);
int nv50_display_early_init(struct drm_device *dev);

4
drivers/gpu/drm/nouveau/nv50_gpio.c
View File

@ -26,6 +26,8 @@
#include "nouveau_drv.h"
#include "nouveau_hw.h"
#include "nv50_display.h"
static void nv50_gpio_isr(struct drm_device *dev);
static int
@ -109,6 +111,8 @@ nv50_gpio_init(struct drm_device *dev)
nv_wr32(dev, 0xe074, 0xffffffff);
}
INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
spin_lock_init(&dev_priv->hpd_state.lock);
nouveau_irq_register(dev, 21, nv50_gpio_isr);
return 0;
}