ARM: ARMv7-M: Add support for exception handling
This patch implements the exception handling for the ARMv7-M architecture (pretty different from the A or R profiles). It bases on work done earlier by Catalin for 2.6.33 but was nearly completely rewritten to use a pt_regs layout compatible to the A profile. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Jonathan Austin <jonathan.austin@arm.com> Tested-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>hifive-unleashed-5.1
Uwe Kleine-König
parent
55bdd69411
commit
19c4d593f0
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@ -339,6 +339,9 @@ ENDPROC(ftrace_stub)
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.align 5
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ENTRY(vector_swi)
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#ifdef CONFIG_CPU_V7M
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v7m_exception_entry
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#else
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0 - r12
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ARM( add r8, sp, #S_PC )
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@ -349,6 +352,7 @@ ENTRY(vector_swi)
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str lr, [sp, #S_PC] @ Save calling PC
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str r8, [sp, #S_PSR] @ Save CPSR
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str r0, [sp, #S_OLD_R0] @ Save OLD_R0
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#endif
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zero_fp
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/*
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@ -5,6 +5,7 @@
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#include <asm/asm-offsets.h>
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#include <asm/errno.h>
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#include <asm/thread_info.h>
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#include <asm/v7m.h>
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@ Bad Abort numbers
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@ -----------------
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@ -44,6 +45,116 @@
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#endif
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.endm
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#ifdef CONFIG_CPU_V7M
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/*
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* ARMv7-M exception entry/exit macros.
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*
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* xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
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* automatically saved on the current stack (32 words) before
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* switching to the exception stack (SP_main).
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*
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* If exception is taken while in user mode, SP_main is
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* empty. Otherwise, SP_main is aligned to 64 bit automatically
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* (CCR.STKALIGN set).
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*
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* Linux assumes that the interrupts are disabled when entering an
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* exception handler and it may BUG if this is not the case. Interrupts
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* are disabled during entry and reenabled in the exit macro.
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*
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* v7m_exception_slow_exit is used when returning from SVC or PendSV.
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* When returning to kernel mode, we don't return from exception.
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*/
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.macro v7m_exception_entry
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@ determine the location of the registers saved by the core during
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@ exception entry. Depending on the mode the cpu was in when the
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@ exception happend that is either on the main or the process stack.
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@ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
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@ was used.
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tst lr, #EXC_RET_STACK_MASK
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mrsne r12, psp
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moveq r12, sp
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@ we cannot rely on r0-r3 and r12 matching the value saved in the
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@ exception frame because of tail-chaining. So these have to be
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@ reloaded.
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ldmia r12!, {r0-r3}
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@ Linux expects to have irqs off. Do it here before taking stack space
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cpsid i
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sub sp, #S_FRAME_SIZE-S_IP
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stmdb sp!, {r0-r11}
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@ load saved r12, lr, return address and xPSR.
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@ r0-r7 are used for signals and never touched from now on. Clobbering
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@ r8-r12 is OK.
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mov r9, r12
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ldmia r9!, {r8, r10-r12}
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@ calculate the original stack pointer value.
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@ r9 currently points to the memory location just above the auto saved
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@ xPSR.
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@ The cpu might automatically 8-byte align the stack. Bit 9
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@ of the saved xPSR specifies if stack aligning took place. In this case
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@ another 32-bit value is included in the stack.
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tst r12, V7M_xPSR_FRAMEPTRALIGN
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addne r9, r9, #4
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@ store saved r12 using str to have a register to hold the base for stm
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str r8, [sp, #S_IP]
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add r8, sp, #S_SP
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@ store r13-r15, xPSR
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stmia r8!, {r9-r12}
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@ store old_r0
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str r0, [r8]
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.endm
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/*
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* PENDSV and SVCALL are configured to have the same exception
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* priorities. As a kernel thread runs at SVCALL execution priority it
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* can never be preempted and so we will never have to return to a
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* kernel thread here.
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*/
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.macro v7m_exception_slow_exit ret_r0
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cpsid i
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ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK
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@ read original r12, sp, lr, pc and xPSR
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add r12, sp, #S_IP
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ldmia r12, {r1-r5}
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@ an exception frame is always 8-byte aligned. To tell the hardware if
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@ the sp to be restored is aligned or not set bit 9 of the saved xPSR
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@ accordingly.
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tst r2, #4
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subne r2, r2, #4
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orrne r5, V7M_xPSR_FRAMEPTRALIGN
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biceq r5, V7M_xPSR_FRAMEPTRALIGN
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@ write basic exception frame
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stmdb r2!, {r1, r3-r5}
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ldmia sp, {r1, r3-r5}
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.if \ret_r0
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stmdb r2!, {r0, r3-r5}
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.else
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stmdb r2!, {r1, r3-r5}
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.endif
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@ restore process sp
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msr psp, r2
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@ restore original r4-r11
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ldmia sp!, {r0-r11}
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@ restore main sp
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add sp, sp, #S_FRAME_SIZE-S_IP
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cpsie i
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bx lr
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.endm
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#endif /* CONFIG_CPU_V7M */
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@
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@ Store/load the USER SP and LR registers by switching to the SYS
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@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
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@ -131,6 +242,18 @@
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rfeia sp!
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.endm
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#ifdef CONFIG_CPU_V7M
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/*
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* Note we don't need to do clrex here as clearing the local monitor is
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* part of each exception entry and exit sequence.
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*/
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.macro restore_user_regs, fast = 0, offset = 0
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.if \offset
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add sp, #\offset
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.endif
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v7m_exception_slow_exit ret_r0 = \fast
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.endm
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#else /* ifdef CONFIG_CPU_V7M */
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.macro restore_user_regs, fast = 0, offset = 0
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clrex @ clear the exclusive monitor
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mov r2, sp
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@ -147,6 +270,7 @@
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add sp, sp, #S_FRAME_SIZE - S_SP
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movs pc, lr @ return & move spsr_svc into cpsr
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.endm
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#endif /* ifdef CONFIG_CPU_V7M / else */
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.macro get_thread_info, rd
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mov \rd, sp
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@ -0,0 +1,143 @@
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/*
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* linux/arch/arm/kernel/entry-v7m.S
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*
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* Copyright (C) 2008 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Low-level vector interface routines for the ARMv7-M architecture
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*/
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#include <asm/memory.h>
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#include <asm/glue.h>
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#include <asm/thread_notify.h>
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#include <asm/v7m.h>
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#include <mach/entry-macro.S>
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#include "entry-header.S"
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#ifdef CONFIG_TRACE_IRQFLAGS
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#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
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#endif
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__invalid_entry:
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v7m_exception_entry
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adr r0, strerr
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mrs r1, ipsr
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mov r2, lr
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bl printk
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mov r0, sp
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bl show_regs
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1: b 1b
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ENDPROC(__invalid_entry)
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strerr: .asciz "\nUnhandled exception: IPSR = %08lx LR = %08lx\n"
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.align 2
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__irq_entry:
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v7m_exception_entry
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@
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@ Invoke the IRQ handler
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@
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mrs r0, ipsr
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ldr r1, =V7M_xPSR_EXCEPTIONNO
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and r0, r1
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sub r0, #16
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mov r1, sp
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stmdb sp!, {lr}
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@ routine called with r0 = irq number, r1 = struct pt_regs *
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bl nvic_do_IRQ
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pop {lr}
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@
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@ Check for any pending work if returning to user
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@
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ldr r1, =BASEADDR_V7M_SCB
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ldr r0, [r1, V7M_SCB_ICSR]
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tst r0, V7M_SCB_ICSR_RETTOBASE
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beq 2f
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get_thread_info tsk
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ldr r2, [tsk, #TI_FLAGS]
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tst r2, #_TIF_WORK_MASK
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beq 2f @ no work pending
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mov r0, #V7M_SCB_ICSR_PENDSVSET
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str r0, [r1, V7M_SCB_ICSR] @ raise PendSV
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2:
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@ registers r0-r3 and r12 are automatically restored on exception
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@ return. r4-r7 were not clobbered in v7m_exception_entry so for
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@ correctness they don't need to be restored. So only r8-r11 must be
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@ restored here. The easiest way to do so is to restore r0-r7, too.
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ldmia sp!, {r0-r11}
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add sp, #S_FRAME_SIZE-S_IP
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cpsie i
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bx lr
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ENDPROC(__irq_entry)
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__pendsv_entry:
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v7m_exception_entry
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ldr r1, =BASEADDR_V7M_SCB
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mov r0, #V7M_SCB_ICSR_PENDSVCLR
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str r0, [r1, V7M_SCB_ICSR] @ clear PendSV
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@ execute the pending work, including reschedule
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get_thread_info tsk
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mov why, #0
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b ret_to_user
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ENDPROC(__pendsv_entry)
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/*
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* Register switch for ARMv7-M processors.
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* r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
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* previous and next are guaranteed not to be the same.
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*/
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ENTRY(__switch_to)
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.fnstart
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.cantunwind
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add ip, r1, #TI_CPU_SAVE
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stmia ip!, {r4 - r11} @ Store most regs on stack
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str sp, [ip], #4
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str lr, [ip], #4
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mov r5, r0
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add r4, r2, #TI_CPU_SAVE
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ldr r0, =thread_notify_head
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mov r1, #THREAD_NOTIFY_SWITCH
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bl atomic_notifier_call_chain
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mov ip, r4
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mov r0, r5
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ldmia ip!, {r4 - r11} @ Load all regs saved previously
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ldr sp, [ip]
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ldr pc, [ip, #4]!
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.fnend
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ENDPROC(__switch_to)
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.data
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.align 8
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/*
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* Vector table (64 words => 256 bytes natural alignment)
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*/
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ENTRY(vector_table)
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.long 0 @ 0 - Reset stack pointer
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.long __invalid_entry @ 1 - Reset
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.long __invalid_entry @ 2 - NMI
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.long __invalid_entry @ 3 - HardFault
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.long __invalid_entry @ 4 - MemManage
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.long __invalid_entry @ 5 - BusFault
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.long __invalid_entry @ 6 - UsageFault
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.long __invalid_entry @ 7 - Reserved
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.long __invalid_entry @ 8 - Reserved
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.long __invalid_entry @ 9 - Reserved
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.long __invalid_entry @ 10 - Reserved
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.long vector_swi @ 11 - SVCall
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.long __invalid_entry @ 12 - Debug Monitor
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.long __invalid_entry @ 13 - Reserved
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.long __pendsv_entry @ 14 - PendSV
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.long __invalid_entry @ 15 - SysTick
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.rept 64 - 16
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.long __irq_entry @ 16..64 - External Interrupts
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.endr
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