add suppport common clock framework for exynos
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRYuw1AAoJEA0Cl+kVi2xq53MP/Rimo8kL9e/dMrgxqvtQ198N
csKzsAvOFSI69x0VupVOGfMSMDmltIaimyljJO3YrUvy+UOS3irWTHqu1JKq8+HX
oaym2KirVFpGjcll4E2nyeZ18vL8Czt0bNPh2QVuHinwbETtAuq0CBfeAQLWA1Xs
I/bbVKryocLwMNd5iqttSwGVwNZz14ceheliSHkneDeTaZJYQ0nSCLL7qmXncRFl
Z1Xe4aZRTdiU8JZiRN6G3Q2UdhcKRwZPSZrftbVpDRBegnaZp6htUszD2GFX3SJH
lV4ifgh9XVawRPE8Op00lX9fEjGe3EDP5kqqFRqht+mvr15vs2eFNiIIYOyjvBDU
GfCK2Ij2QaUCiIweJOcO5SGkLKYqyVg+G5k7Z5M5FGwwBhEdZRPkZE++9cWG8K/m
ziuJxAl9fK47NwUk4oz15e6JD6gFbEwqYf1f7RdvdRBiclarIuk2rha9BsoeOFM3
LBpGhWW4rcwEH87e0MjkvoopYl4ZHLtiZYk6cEg0rmAxKLvQjdZCZM+A707RG6DC
CZiY6Iu5pSOIz4FweY42mXaANkdBlzn4r7/cPJj7S4umQlkEjYtwXEEziK50lc+g
b7aZEvztQhFDw3lHhFeR44FCy7a1r5NjAZASshHJ72h3xNXrp+9bbugpbkdQVUKj
tpL2eMZQn/lK6T1h8SwE
=JEIy
-----END PGP SIGNATURE-----
Merge tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
add suppport common clock framework for exynos
* tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (73 commits)
ARM: EXYNOS: fix compilation error introduced due to common clock migration
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
clk: exynos4: export clocks required for fimc-is
clk: samsung: Fix compilation error
clk: exynos5250: register display block gate clocks to common clock framework
clk: exynos4: Add support for SoC-specific register save list
clk: exynos4: Add missing registers to suspend save list
clk: exynos4: Remove E4X12 prefix from SRC_DMC register
clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register
clk: exynos4: Add E4210 prefix to LCD1 clock registers
clk: exynos4: Remove SoC-specific registers from save list
clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions
clk: exynos4: Define {E,V}PLL registers
clk: exynos4: Add missing mout_sata on Exynos4210
clk: exynos4: Add missing CMU_TOP and ISP clocks
clk: exynos4: Add G3D clocks
clk: exynos4: Add camera related clock definitions
clk: exynos4: Export mout_core clock of Exynos4210
clk: samsung: Remove unimplemented ops for pll
clk: exynos4: Export clocks used by exynos cpufreq drivers
...
[arnd: add missing #address-cells property in mshc DT node]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
hifive-unleashed-5.1
Arnd Bergmann
commit
19ce4f4a03
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@ -0,0 +1,288 @@
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* Samsung Exynos4 Clock Controller
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The Exynos4 clock controller generates and supplies clock to various controllers
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within the Exynos4 SoC. The clock binding described here is applicable to all
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SoC's in the Exynos4 family.
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||||
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Required Properties:
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- comptible: should be one of the following.
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- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
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- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume. Some of the clocks are available only on a particular
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Exynos4 SoC and this is specified where applicable.
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[Core Clocks]
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Clock ID SoC (if specific)
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-----------------------------------------------
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xxti 1
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xusbxti 2
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fin_pll 3
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fout_apll 4
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fout_mpll 5
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fout_epll 6
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fout_vpll 7
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sclk_apll 8
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sclk_mpll 9
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sclk_epll 10
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sclk_vpll 11
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arm_clk 12
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aclk200 13
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aclk100 14
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aclk160 15
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aclk133 16
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mout_mpll_user_t 17 Exynos4x12
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mout_mpll_user_c 18 Exynos4x12
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mout_core 19
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mout_apll 20
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[Clock Gate for Special Clocks]
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Clock ID SoC (if specific)
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-----------------------------------------------
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sclk_fimc0 128
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sclk_fimc1 129
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sclk_fimc2 130
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sclk_fimc3 131
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sclk_cam0 132
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sclk_cam1 133
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sclk_csis0 134
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sclk_csis1 135
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sclk_hdmi 136
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sclk_mixer 137
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sclk_dac 138
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sclk_pixel 139
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sclk_fimd0 140
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sclk_mdnie0 141 Exynos4412
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sclk_mdnie_pwm0 12 142 Exynos4412
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sclk_mipi0 143
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sclk_audio0 144
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sclk_mmc0 145
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sclk_mmc1 146
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sclk_mmc2 147
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sclk_mmc3 148
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sclk_mmc4 149
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sclk_sata 150 Exynos4210
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sclk_uart0 151
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sclk_uart1 152
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sclk_uart2 153
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sclk_uart3 154
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sclk_uart4 155
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sclk_audio1 156
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sclk_audio2 157
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sclk_spdif 158
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sclk_spi0 159
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sclk_spi1 160
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sclk_spi2 161
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sclk_slimbus 162
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sclk_fimd1 163 Exynos4210
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sclk_mipi1 164 Exynos4210
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sclk_pcm1 165
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sclk_pcm2 166
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sclk_i2s1 167
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sclk_i2s2 168
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sclk_mipihsi 169 Exynos4412
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sclk_mfc 170
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sclk_pcm0 171
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sclk_g3d 172
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sclk_pwm_isp 173 Exynos4x12
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sclk_spi0_isp 174 Exynos4x12
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sclk_spi1_isp 175 Exynos4x12
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sclk_uart_isp 176 Exynos4x12
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[Peripheral Clock Gates]
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Clock ID SoC (if specific)
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-----------------------------------------------
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fimc0 256
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fimc1 257
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fimc2 258
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fimc3 259
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csis0 260
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csis1 261
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jpeg 262
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smmu_fimc0 263
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smmu_fimc1 264
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smmu_fimc2 265
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smmu_fimc3 266
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smmu_jpeg 267
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vp 268
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mixer 269
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tvenc 270 Exynos4210
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hdmi 271
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smmu_tv 272
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mfc 273
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smmu_mfcl 274
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smmu_mfcr 275
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g3d 276
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g2d 277 Exynos4210
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rotator 278 Exynos4210
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mdma 279 Exynos4210
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smmu_g2d 280 Exynos4210
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smmu_rotator 281 Exynos4210
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smmu_mdma 282 Exynos4210
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fimd0 283
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mie0 284
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mdnie0 285 Exynos4412
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dsim0 286
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smmu_fimd0 287
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fimd1 288 Exynos4210
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mie1 289 Exynos4210
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dsim1 290 Exynos4210
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smmu_fimd1 291 Exynos4210
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pdma0 292
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pdma1 293
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pcie_phy 294
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sata_phy 295 Exynos4210
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tsi 296
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sdmmc0 297
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sdmmc1 298
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sdmmc2 299
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sdmmc3 300
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sdmmc4 301
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sata 302 Exynos4210
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sromc 303
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usb_host 304
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usb_device 305
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pcie 306
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onenand 307
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nfcon 308
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smmu_pcie 309
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gps 310
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smmu_gps 311
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uart0 312
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uart1 313
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uart2 314
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uart3 315
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uart4 316
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i2c0 317
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i2c1 318
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i2c2 319
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i2c3 320
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i2c4 321
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i2c5 322
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i2c6 323
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i2c7 324
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i2c_hdmi 325
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tsadc 326
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spi0 327
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spi1 328
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spi2 329
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i2s1 330
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i2s2 331
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pcm0 332
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i2s0 333
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pcm1 334
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pcm2 335
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pwm 336
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slimbus 337
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spdif 338
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ac97 339
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modemif 340
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chipid 341
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sysreg 342
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hdmi_cec 343
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mct 344
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wdt 345
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rtc 346
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keyif 347
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audss 348
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mipi_hsi 349 Exynos4210
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mdma2 350 Exynos4210
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pixelasyncm0 351
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pixelasyncm1 352
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fimc_lite0 353 Exynos4x12
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fimc_lite1 354 Exynos4x12
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ppmuispx 355 Exynos4x12
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ppmuispmx 356 Exynos4x12
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fimc_isp 357 Exynos4x12
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fimc_drc 358 Exynos4x12
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fimc_fd 359 Exynos4x12
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mcuisp 360 Exynos4x12
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gicisp 361 Exynos4x12
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smmu_isp 362 Exynos4x12
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smmu_drc 363 Exynos4x12
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smmu_fd 364 Exynos4x12
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smmu_lite0 365 Exynos4x12
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smmu_lite1 366 Exynos4x12
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mcuctl_isp 367 Exynos4x12
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mpwm_isp 368 Exynos4x12
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i2c0_isp 369 Exynos4x12
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i2c1_isp 370 Exynos4x12
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mtcadc_isp 371 Exynos4x12
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pwm_isp 372 Exynos4x12
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wdt_isp 373 Exynos4x12
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uart_isp 374 Exynos4x12
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asyncaxim 375 Exynos4x12
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smmu_ispcx 376 Exynos4x12
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spi0_isp 377 Exynos4x12
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spi1_isp 378 Exynos4x12
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pwm_isp_sclk 379 Exynos4x12
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spi0_isp_sclk 380 Exynos4x12
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spi1_isp_sclk 381 Exynos4x12
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uart_isp_sclk 382 Exynos4x12
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[Mux Clocks]
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Clock ID SoC (if specific)
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-----------------------------------------------
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mout_fimc0 384
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mout_fimc1 385
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mout_fimc2 386
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mout_fimc3 387
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mout_cam0 388
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mout_cam1 389
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mout_csis0 390
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mout_csis1 391
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mout_g3d0 392
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mout_g3d1 393
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mout_g3d 394
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aclk400_mcuisp 395 Exynos4x12
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[Div Clocks]
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Clock ID SoC (if specific)
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-----------------------------------------------
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div_isp0 450 Exynos4x12
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div_isp1 451 Exynos4x12
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div_mcuisp0 452 Exynos4x12
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div_mcuisp1 453 Exynos4x12
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div_aclk200 454 Exynos4x12
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div_aclk400_mcuisp 455 Exynos4x12
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Example 1: An example of a clock controller node is listed below.
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clock: clock-controller@0x10030000 {
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compatible = "samsung,exynos4210-clock";
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reg = <0x10030000 0x20000>;
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#clock-cells = <1>;
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};
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Example 2: UART controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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serial@13820000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13820000 0x100>;
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interrupts = <0 54 0>;
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clocks = <&clock 314>, <&clock 153>;
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clock-names = "uart", "clk_uart_baud0";
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};
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@ -0,0 +1,177 @@
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* Samsung Exynos5250 Clock Controller
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The Exynos5250 clock controller generates and supplies clock to various
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controllers within the Exynos5250 SoC.
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||||
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Required Properties:
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||||
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- comptible: should be one of the following.
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- "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
|
||||
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- reg: physical base address of the controller and length of memory mapped
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||||
region.
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- #clock-cells: should be 1.
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume.
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[Core Clocks]
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Clock ID
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----------------------------
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fin_pll 1
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[Clock Gate for Special Clocks]
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Clock ID
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----------------------------
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sclk_cam_bayer 128
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sclk_cam0 129
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sclk_cam1 130
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sclk_gscl_wa 131
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sclk_gscl_wb 132
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sclk_fimd1 133
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sclk_mipi1 134
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sclk_dp 135
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sclk_hdmi 136
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sclk_pixel 137
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sclk_audio0 138
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sclk_mmc0 139
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sclk_mmc1 140
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sclk_mmc2 141
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sclk_mmc3 142
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sclk_sata 143
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sclk_usb3 144
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sclk_jpeg 145
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sclk_uart0 146
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sclk_uart1 147
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sclk_uart2 148
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sclk_uart3 149
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sclk_pwm 150
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sclk_audio1 151
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sclk_audio2 152
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sclk_spdif 153
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sclk_spi0 154
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sclk_spi1 155
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sclk_spi2 156
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[Peripheral Clock Gates]
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Clock ID
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----------------------------
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gscl0 256
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gscl1 257
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gscl2 258
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gscl3 259
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gscl_wa 260
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gscl_wb 261
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smmu_gscl0 262
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smmu_gscl1 263
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smmu_gscl2 264
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smmu_gscl3 265
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mfc 266
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smmu_mfcl 267
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smmu_mfcr 268
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rotator 269
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jpeg 270
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mdma1 271
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smmu_rotator 272
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smmu_jpeg 273
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smmu_mdma1 274
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pdma0 275
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pdma1 276
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sata 277
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usbotg 278
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mipi_hsi 279
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sdmmc0 280
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sdmmc1 281
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sdmmc2 282
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sdmmc3 283
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sromc 284
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usb2 285
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usb3 286
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sata_phyctrl 287
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sata_phyi2c 288
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uart0 289
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uart1 290
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uart2 291
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uart3 292
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uart4 293
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i2c0 294
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i2c1 295
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i2c2 296
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i2c3 297
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i2c4 298
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i2c5 299
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i2c6 300
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i2c7 301
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i2c_hdmi 302
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adc 303
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spi0 304
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spi1 305
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spi2 306
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i2s1 307
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i2s2 308
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pcm1 309
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pcm2 310
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pwm 311
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spdif 312
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ac97 313
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hsi2c0 314
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hsi2c1 315
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hs12c2 316
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hs12c3 317
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chipid 318
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sysreg 319
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pmu 320
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cmu_top 321
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cmu_core 322
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cmu_mem 323
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tzpc0 324
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tzpc1 325
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tzpc2 326
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tzpc3 327
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tzpc4 328
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tzpc5 329
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tzpc6 330
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tzpc7 331
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tzpc8 332
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tzpc9 333
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hdmi_cec 334
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mct 335
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wdt 336
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rtc 337
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tmu 338
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fimd1 339
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mie1 340
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dsim0 341
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dp 342
|
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mixer 343
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hdmi 345
|
||||
|
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Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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||||
};
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|
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Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@13820000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
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interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
* Samsung Exynos5440 Clock Controller
|
||||
|
||||
The Exynos5440 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5440 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be "samsung,exynos5440-clock".
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
xtal 1
|
||||
arm_clk 2
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
spi_baud 16
|
||||
pb0_250 17
|
||||
pr0_250 18
|
||||
pr1_250 19
|
||||
b_250 20
|
||||
b_125 21
|
||||
b_200 22
|
||||
sata 23
|
||||
usb 24
|
||||
gmac0 25
|
||||
cs250 26
|
||||
pb0_250_o 27
|
||||
pr0_250_o 28
|
||||
pr1_250_o 29
|
||||
b_250_o 30
|
||||
b_125_o 31
|
||||
b_200_o 32
|
||||
sata_o 33
|
||||
usb_o 34
|
||||
gmac0_o 35
|
||||
cs250_o 36
|
||||
|
||||
Example: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5440-clock";
|
||||
reg = <0x160000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -21,3 +21,24 @@ Required properties:
|
|||
|
||||
- samsung,mfc-l : Base address of the second memory bank used by MFC
|
||||
for DMA contiguous memory allocation and its size.
|
||||
|
||||
Optional properties:
|
||||
- samsung,power-domain : power-domain property defined with a phandle
|
||||
to respective power domain.
|
||||
|
||||
Example:
|
||||
SoC specific DT entry:
|
||||
|
||||
mfc: codec@13400000 {
|
||||
compatible = "samsung,mfc-v5";
|
||||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
};
|
||||
|
||||
Board specific DT entry:
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,40 @@
|
|||
Samsung Exynos SoC USB controller
|
||||
|
||||
The USB devices interface with USB controllers on Exynos SOCs.
|
||||
The device node has following properties.
|
||||
|
||||
EHCI
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos4210-ehci" for USB 2.0
|
||||
EHCI controller in host mode.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
|
||||
Optional properties:
|
||||
- samsung,vbus-gpio: if present, specifies the GPIO that
|
||||
needs to be pulled up for the bus to be powered.
|
||||
|
||||
Example:
|
||||
|
||||
usb@12110000 {
|
||||
compatible = "samsung,exynos4210-ehci";
|
||||
reg = <0x12110000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
|
||||
};
|
||||
|
||||
OHCI
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos4210-ohci" for USB 2.0
|
||||
OHCI companion controller in host mode.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
|
||||
Example:
|
||||
usb@12120000 {
|
||||
compatible = "samsung,exynos4210-ohci";
|
||||
reg = <0x12120000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
};
|
||||
|
|
@ -866,6 +866,7 @@ config ARCH_EXYNOS
|
|||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
|
|
|
|||
|
|
@ -42,7 +42,10 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
|
|||
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
|
||||
exynos4210-smdkv310.dtb \
|
||||
exynos4210-trats.dtb \
|
||||
exynos4412-odroidx.dtb \
|
||||
exynos4412-smdk4412.dtb \
|
||||
exynos4412-origen.dtb \
|
||||
exynos5250-arndale.dtb \
|
||||
exynos5250-smdk5250.dtb \
|
||||
exynos5250-snow.dtb \
|
||||
exynos5440-ssdk5440.dtb
|
||||
|
|
|
|||
|
|
@ -24,6 +24,144 @@
|
|||
samsung,i2c-max-bus-freq = <378000>;
|
||||
gpios = <&gpb3 0 2 3 0>,
|
||||
<&gpb3 1 2 3 0>;
|
||||
|
||||
max77686@09 {
|
||||
compatible = "maxim,max77686";
|
||||
reg = <0x09>;
|
||||
|
||||
voltage-regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "P1.0V_LDO_OUT1";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "P1.8V_LDO_OUT2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "P1.8V_LDO_OUT3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "P1.1V_LDO_OUT7";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "P1.0V_LDO_OUT8";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "P1.8V_LDO_OUT10";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "P3.0V_LDO_OUT12";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "P1.8V_LDO_OUT14";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "P1.0V_LDO_OUT15";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "P1.8V_LDO_OUT16";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "P1.8V_BUCK_OUT5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "P1.35V_BUCK_OUT6";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck7_reg: BUCK7 {
|
||||
regulator-name = "P2.0V_BUCK_OUT7";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck8_reg: BUCK8 {
|
||||
regulator-name = "P2.85V_BUCK_OUT8";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@12C70000 {
|
||||
|
|
|
|||
|
|
@ -86,6 +86,8 @@
|
|||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 43 0>;
|
||||
clocks = <&clock 345>;
|
||||
clock-names = "watchdog";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -93,6 +95,8 @@
|
|||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x10070000 0x100>;
|
||||
interrupts = <0 44 0>, <0 45 0>;
|
||||
clocks = <&clock 346>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -100,6 +104,8 @@
|
|||
compatible = "samsung,s5pv210-keypad";
|
||||
reg = <0x100A0000 0x100>;
|
||||
interrupts = <0 109 0>;
|
||||
clocks = <&clock 347>;
|
||||
clock-names = "keypad";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -107,6 +113,8 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12510000 0x100>;
|
||||
interrupts = <0 73 0>;
|
||||
clocks = <&clock 297>, <&clock 145>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -114,6 +122,8 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12520000 0x100>;
|
||||
interrupts = <0 74 0>;
|
||||
clocks = <&clock 298>, <&clock 146>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -121,6 +131,8 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12530000 0x100>;
|
||||
interrupts = <0 75 0>;
|
||||
clocks = <&clock 299>, <&clock 147>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -128,6 +140,16 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12540000 0x100>;
|
||||
interrupts = <0 76 0>;
|
||||
clocks = <&clock 300>, <&clock 148>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mfc: codec@13400000 {
|
||||
compatible = "samsung,mfc-v5";
|
||||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -135,6 +157,8 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13800000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
clocks = <&clock 312>, <&clock 151>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -142,6 +166,8 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13810000 0x100>;
|
||||
interrupts = <0 53 0>;
|
||||
clocks = <&clock 313>, <&clock 152>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -149,6 +175,8 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -156,6 +184,8 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13830000 0x100>;
|
||||
interrupts = <0 55 0>;
|
||||
clocks = <&clock 315>, <&clock 154>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -165,6 +195,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13860000 0x100>;
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock 317>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -174,6 +206,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13870000 0x100>;
|
||||
interrupts = <0 59 0>;
|
||||
clocks = <&clock 318>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -183,6 +217,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13880000 0x100>;
|
||||
interrupts = <0 60 0>;
|
||||
clocks = <&clock 319>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -192,6 +228,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13890000 0x100>;
|
||||
interrupts = <0 61 0>;
|
||||
clocks = <&clock 320>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -201,6 +239,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138A0000 0x100>;
|
||||
interrupts = <0 62 0>;
|
||||
clocks = <&clock 321>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -210,6 +250,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138B0000 0x100>;
|
||||
interrupts = <0 63 0>;
|
||||
clocks = <&clock 322>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -219,6 +261,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138C0000 0x100>;
|
||||
interrupts = <0 64 0>;
|
||||
clocks = <&clock 323>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -228,6 +272,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138D0000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 324>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -239,6 +285,8 @@
|
|||
rx-dma-channel = <&pdma0 6>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 327>, <&clock 159>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -250,6 +298,8 @@
|
|||
rx-dma-channel = <&pdma1 6>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 328>, <&clock 160>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -261,6 +311,8 @@
|
|||
rx-dma-channel = <&pdma0 8>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 329>, <&clock 161>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -275,6 +327,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12680000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 292>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -284,6 +338,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12690000 0x1000>;
|
||||
interrupts = <0 36 0>;
|
||||
clocks = <&clock 293>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -293,6 +349,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12850000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 279>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
|
|
|
|||
|
|
@ -57,6 +57,12 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -121,4 +127,16 @@
|
|||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -43,6 +43,12 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -189,4 +195,16 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -289,4 +289,16 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -55,6 +55,8 @@
|
|||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
clocks = <&clock 3>, <&clock 344>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -69,6 +71,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4210-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,exynos4210-pinctrl";
|
||||
reg = <0x11400000 0x1000>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* Hardkernel's Exynos4412 based ODROID-X board device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
|
||||
*
|
||||
* Device tree source file for Hardkernel's ODROID-X board which is based on
|
||||
* Samsung's Exynos4412 SoC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4412.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Hardkernel ODROID-X board based on Exynos4412";
|
||||
compatible = "hardkernel,odroid-x", "samsung,exynos4412";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led1 {
|
||||
label = "led1:heart";
|
||||
gpios = <&gpc1 0 1>;
|
||||
default-state = "on";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
led2 {
|
||||
label = "led2:mmc0";
|
||||
gpios = <&gpc1 2 1>;
|
||||
default-state = "on";
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator_p3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "p3v3_en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpa1 1 1>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
rtc@10070000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13810000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13820000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,432 @@
|
|||
/*
|
||||
* Insignal's Exynos4412 based Origen board device tree source
|
||||
*
|
||||
* Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Device tree source file for Insignal's Origen board which is based on
|
||||
* Samsung's Exynos4412 SoC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4412.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Insignal Origen evaluation board based on Exynos4412";
|
||||
compatible = "insignal,origen4412", "samsung,exynos4412";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs ="console=ttySAC2,115200";
|
||||
};
|
||||
|
||||
mmc_reg: voltage-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VMEM_VDD_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
gpio = <&gpx1 1 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <&mmc_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13810000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13820000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@13860000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <20000>;
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
s5m8767_pmic@66 {
|
||||
compatible = "samsung,s5m8767-pmic";
|
||||
reg = <0x66>;
|
||||
|
||||
s5m8767,pmic-buck-default-dvs-idx = <3>;
|
||||
|
||||
s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
|
||||
<&gpx2 4 0>,
|
||||
<&gpx2 5 0>;
|
||||
|
||||
s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
|
||||
<&gpm3 6 0>,
|
||||
<&gpm3 7 0>;
|
||||
|
||||
s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>;
|
||||
|
||||
s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
|
||||
<1100000>, <1100000>,
|
||||
<1100000>, <1100000>,
|
||||
<1100000>, <1100000>;
|
||||
|
||||
s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>;
|
||||
|
||||
regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "VDD_ALIVE";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "VDDQ_M12";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "VDDIOAP_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "VDDQ_PRE";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo5_reg: LDO5 {
|
||||
regulator-name = "VDD18_2M";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "VDD10_MPLL";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "VDD10_XPLL";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "VDD10_MIPI";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo9_reg: LDO9 {
|
||||
regulator-name = "VDD33_LCD";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "VDD18_MIPI";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
regulator-name = "VDD18_ABB1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "VDD33_UOTG";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo13_reg: LDO13 {
|
||||
regulator-name = "VDDIOPERI_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "VDD18_ABB02";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "VDD10_USH";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "VDD18_HSIC";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo17_reg: LDO17 {
|
||||
regulator-name = "VDDIOAP_MMC012_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo18_reg: LDO18 {
|
||||
regulator-name = "VDDIOPERI_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo19_reg: LDO19 {
|
||||
regulator-name = "DVDD25";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo20_reg: LDO20 {
|
||||
regulator-name = "VDD28_CAM";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo21_reg: LDO21 {
|
||||
regulator-name = "VDD28_AF";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo22_reg: LDO22 {
|
||||
regulator-name = "VDDA28_2M";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo23_reg: LDO23 {
|
||||
regulator-name = "VDD28_TF";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo24_reg: LDO24 {
|
||||
regulator-name = "VDD33_A31";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo25_reg: LDO25 {
|
||||
regulator-name = "VDD18_CAM";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo26_reg: LDO26 {
|
||||
regulator-name = "VDD18_A31";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo27_reg: LDO27 {
|
||||
regulator-name = "GPS_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo28_reg: LDO28 {
|
||||
regulator-name = "DVDD12";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "vdd_m12";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "vdd12_5m";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck9_reg: BUCK9 {
|
||||
regulator-name = "vddf28_emmc";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -27,6 +27,19 @@
|
|||
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -42,4 +55,16 @@
|
|||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@
|
|||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>, <6 0>, <7 0>;
|
||||
clocks = <&clock 3>, <&clock 344>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -36,6 +36,12 @@
|
|||
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4412-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,exynos4x12-pinctrl";
|
||||
reg = <0x11400000 0x1000>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,129 @@
|
|||
/*
|
||||
* Samsung's Exynos5250 based Arndale board device tree source
|
||||
*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos5250.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Insignal Arndale evaluation board based on EXYNOS5250";
|
||||
compatible = "insignal,arndale", "samsung,exynos5250";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x80000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttySAC2,115200";
|
||||
};
|
||||
|
||||
i2c@12C60000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C70000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C80000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C90000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CA0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CB0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CC0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CD0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@121D0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dwmmc_0: dwmmc0@12200000 {
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
|
||||
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
|
||||
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
|
||||
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
|
||||
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
|
||||
};
|
||||
};
|
||||
|
||||
dwmmc_1: dwmmc1@12210000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dwmmc_2: dwmmc2@12220000 {
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
|
||||
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
|
||||
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
|
||||
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
|
||||
};
|
||||
};
|
||||
|
||||
dwmmc_3: dwmmc3@12230000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_0: spi@12d20000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_1: spi@12d30000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_2: spi@12d40000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -231,4 +231,24 @@
|
|||
samsung,i2s-controller = <&i2s0>;
|
||||
samsung,audio-codec = <&wm8994>;
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
|
||||
};
|
||||
|
||||
dp-controller {
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -40,4 +40,15 @@
|
|||
<&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
samsung,vbus-gpio = <&gpx1 1 1 3 3>;
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -46,6 +46,22 @@
|
|||
i2c8 = &i2c_8;
|
||||
};
|
||||
|
||||
pd_gsc: gsc-power-domain@0x10044000 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044000 0x20>;
|
||||
};
|
||||
|
||||
pd_mfc: mfc-power-domain@0x10044040 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044040 0x20>;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic:interrupt-controller@10481000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -77,6 +93,8 @@
|
|||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
clocks = <&clock 1>, <&clock 335>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -95,54 +113,71 @@
|
|||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x101D0000 0x100>;
|
||||
interrupts = <0 42 0>;
|
||||
clocks = <&clock 336>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
codec@11000000 {
|
||||
compatible = "samsung,mfc-v6";
|
||||
reg = <0x11000000 0x10000>;
|
||||
interrupts = <0 96 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x101E0000 0x100>;
|
||||
interrupts = <0 43 0>, <0 44 0>;
|
||||
clocks = <&clock 337>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
|
||||
tmu@10060000 {
|
||||
compatible = "samsung,exynos5250-tmu";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 338>;
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
serial@12C00000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 51 0>;
|
||||
clocks = <&clock 289>, <&clock 146>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C10000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C10000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
clocks = <&clock 290>, <&clock 147>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C20000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C20000 0x100>;
|
||||
interrupts = <0 53 0>;
|
||||
clocks = <&clock 291>, <&clock 148>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C30000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C30000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 292>, <&clock 149>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
sata@122F0000 {
|
||||
compatible = "samsung,exynos5-sata-ahci";
|
||||
reg = <0x122F0000 0x1ff>;
|
||||
interrupts = <0 115 0>;
|
||||
clocks = <&clock 277>, <&clock 143>;
|
||||
clock-names = "sata", "sclk_sata";
|
||||
};
|
||||
|
||||
sata-phy@12170000 {
|
||||
|
|
@ -156,6 +191,8 @@
|
|||
interrupts = <0 56 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 294>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_1: i2c@12C70000 {
|
||||
|
|
@ -164,6 +201,8 @@
|
|||
interrupts = <0 57 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 295>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_2: i2c@12C80000 {
|
||||
|
|
@ -172,6 +211,8 @@
|
|||
interrupts = <0 58 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 296>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_3: i2c@12C90000 {
|
||||
|
|
@ -180,6 +221,8 @@
|
|||
interrupts = <0 59 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 297>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_4: i2c@12CA0000 {
|
||||
|
|
@ -188,6 +231,8 @@
|
|||
interrupts = <0 60 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 298>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_5: i2c@12CB0000 {
|
||||
|
|
@ -196,6 +241,8 @@
|
|||
interrupts = <0 61 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 299>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_6: i2c@12CC0000 {
|
||||
|
|
@ -204,6 +251,8 @@
|
|||
interrupts = <0 62 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 300>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_7: i2c@12CD0000 {
|
||||
|
|
@ -212,6 +261,8 @@
|
|||
interrupts = <0 63 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 301>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c_8: i2c@12CE0000 {
|
||||
|
|
@ -220,6 +271,8 @@
|
|||
interrupts = <0 64 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 302>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c@121D0000 {
|
||||
|
|
@ -227,6 +280,8 @@
|
|||
reg = <0x121D0000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 288>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
spi_0: spi@12d20000 {
|
||||
|
|
@ -238,6 +293,8 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 304>, <&clock 154>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
spi_1: spi@12d30000 {
|
||||
|
|
@ -249,6 +306,8 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 305>, <&clock 155>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
spi_2: spi@12d40000 {
|
||||
|
|
@ -260,6 +319,8 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 306>, <&clock 156>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
dwmmc_0: dwmmc0@12200000 {
|
||||
|
|
@ -268,6 +329,8 @@
|
|||
interrupts = <0 75 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 280>, <&clock 139>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_1: dwmmc1@12210000 {
|
||||
|
|
@ -276,6 +339,8 @@
|
|||
interrupts = <0 76 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 281>, <&clock 140>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_2: dwmmc2@12220000 {
|
||||
|
|
@ -284,6 +349,8 @@
|
|||
interrupts = <0 77 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 282>, <&clock 141>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_3: dwmmc3@12230000 {
|
||||
|
|
@ -292,6 +359,8 @@
|
|||
interrupts = <0 78 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 283>, <&clock 142>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
i2s0: i2s@03830000 {
|
||||
|
|
@ -323,6 +392,18 @@
|
|||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
compatible = "samsung,exynos4210-ehci";
|
||||
reg = <0x12110000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
};
|
||||
|
||||
usb@12120000 {
|
||||
compatible = "samsung,exynos4210-ohci";
|
||||
reg = <0x12120000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
};
|
||||
|
||||
amba {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -334,6 +415,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121A0000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 275>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -343,6 +426,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121B0000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 276>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -352,6 +437,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 33 0>;
|
||||
clocks = <&clock 271>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
|
|
@ -361,6 +448,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x11C10000 0x1000>;
|
||||
interrupts = <0 124 0>;
|
||||
clocks = <&clock 271>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
|
|
@ -614,34 +703,51 @@
|
|||
};
|
||||
};
|
||||
|
||||
|
||||
gsc_0: gsc@0x13e00000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e00000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 256>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_1: gsc@0x13e10000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e10000 0x1000>;
|
||||
interrupts = <0 86 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 257>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_2: gsc@0x13e20000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e20000 0x1000>;
|
||||
interrupts = <0 87 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 258>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_3: gsc@0x13e30000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e30000 0x1000>;
|
||||
interrupts = <0 88 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 259>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
hdmi {
|
||||
compatible = "samsung,exynos5-hdmi";
|
||||
reg = <0x14530000 0x70000>;
|
||||
interrupts = <0 95 0>;
|
||||
clocks = <&clock 333>, <&clock 136>, <&clock 137>,
|
||||
<&clock 333>, <&clock 333>;
|
||||
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
||||
"sclk_hdmiphy", "hdmiphy";
|
||||
};
|
||||
|
||||
mixer {
|
||||
|
|
@ -649,4 +755,18 @@
|
|||
reg = <0x14450000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
};
|
||||
|
||||
dp-controller {
|
||||
compatible = "samsung,exynos5-dp";
|
||||
reg = <0x145b0000 0x1000>;
|
||||
interrupts = <10 3>;
|
||||
interrupt-parent = <&combiner>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dptx-phy {
|
||||
reg = <0x10040720>;
|
||||
samsung,enable-mask = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,19 +28,10 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@F0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@100000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc {
|
||||
status = "disabled";
|
||||
fixed-rate-clocks {
|
||||
xtal {
|
||||
compatible = "samsung,clock-xtal";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,6 +16,12 @@
|
|||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
clock: clock-controller@0x160000 {
|
||||
compatible = "samsung,exynos5440-clock";
|
||||
reg = <0x160000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic:interrupt-controller@2E0000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -24,55 +30,51 @@
|
|||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <1>;
|
||||
};
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <2>;
|
||||
};
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
common {
|
||||
compatible = "samsung,exynos5440";
|
||||
|
||||
timer {
|
||||
compatible = "arm,cortex-a15-timer",
|
||||
"arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
serial@B0000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xB0000 0x1000>;
|
||||
interrupts = <0 2 0>;
|
||||
clocks = <&clock 21>, <&clock 21>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@C0000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xC0000 0x1000>;
|
||||
interrupts = <0 3 0>;
|
||||
clocks = <&clock 21>, <&clock 21>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
spi {
|
||||
|
|
@ -83,6 +85,8 @@
|
|||
rx-dma-channel = <&pdma0 4>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>, <&clock 16>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
|
|
@ -110,25 +114,31 @@
|
|||
};
|
||||
|
||||
i2c@F0000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
compatible = "samsung,exynos5440-i2c";
|
||||
reg = <0xF0000 0x1000>;
|
||||
interrupts = <0 5 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c@100000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
compatible = "samsung,exynos5440-i2c";
|
||||
reg = <0x100000 0x1000>;
|
||||
interrupts = <0 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <0 1 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
amba {
|
||||
|
|
@ -142,6 +152,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -151,6 +163,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -161,5 +175,7 @@
|
|||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <0 17 0>, <0 16 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ config SOC_EXYNOS5250
|
|||
bool "SAMSUNG EXYNOS5250"
|
||||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
select S5P_DEV_MFC
|
||||
|
|
@ -405,6 +406,7 @@ config MACH_EXYNOS4_DT
|
|||
select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
|
||||
select PINCTRL
|
||||
select PINCTRL_EXYNOS
|
||||
select S5P_DEV_MFC
|
||||
select USE_OF
|
||||
help
|
||||
Machine support for Samsung Exynos4 machine with device tree enabled.
|
||||
|
|
|
|||
|
|
@ -13,10 +13,6 @@ obj- :=
|
|||
# Core
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += common.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
|
||||
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,35 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Header file for exynos4 clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H __FILE__
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
extern struct clksrc_clk exynos4_clk_aclk_133;
|
||||
extern struct clksrc_clk exynos4_clk_mout_mpll;
|
||||
|
||||
extern struct clksrc_sources exynos4_clkset_mout_corebus;
|
||||
extern struct clksrc_sources exynos4_clkset_group;
|
||||
|
||||
extern struct clk *exynos4_clkset_aclk_top_list[];
|
||||
extern struct clk *exynos4_clkset_group_list[];
|
||||
|
||||
extern struct clksrc_sources exynos4_clkset_mout_g2d0;
|
||||
extern struct clksrc_sources exynos4_clkset_mout_g2d1;
|
||||
|
||||
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4210 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4210_clock_save[] = {
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
/* nothing here yet */
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d0",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d0,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d1",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d1,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clk *exynos4210_clkset_mout_g2d_list[] = {
|
||||
[0] = &exynos4210_clk_mout_g2d0.clk,
|
||||
[1] = &exynos4210_clk_mout_g2d1.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources exynos4210_clkset_mout_g2d = {
|
||||
.sources = exynos4210_clkset_mout_g2d_list,
|
||||
.nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
|
||||
};
|
||||
|
||||
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
{
|
||||
.clk = {
|
||||
.name = "sclk_sata",
|
||||
.id = -1,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_corebus,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clksrc_mask_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &exynos4_clkset_group,
|
||||
.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimg2d",
|
||||
},
|
||||
.sources = &exynos4210_clkset_mout_g2d,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
{
|
||||
.name = "sataphy",
|
||||
.id = -1,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sata",
|
||||
.id = -1,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.9",
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.11",
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "fimg2d",
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4210_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4210_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4210_clock_suspend NULL
|
||||
#define exynos4210_clock_resume NULL
|
||||
#endif
|
||||
|
||||
static struct syscore_ops exynos4210_clock_syscore_ops = {
|
||||
.suspend = exynos4210_clock_suspend,
|
||||
.resume = exynos4210_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4210_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 8;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4210_clock_syscore_ops);
|
||||
}
|
||||
|
|
@ -1,201 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4212 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4212_clock_save[] = {
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clk *clk_src_mpll_user_list[] = {
|
||||
[0] = &clk_fin_mpll,
|
||||
[1] = &exynos4_clk_mout_mpll.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clk_src_mpll_user = {
|
||||
.sources = clk_src_mpll_user_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_mout_mpll_user = {
|
||||
.clk = {
|
||||
.name = "mout_mpll_user",
|
||||
},
|
||||
.sources = &clk_src_mpll_user,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d0",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d0,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d1",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d1,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
|
||||
[0] = &exynos4x12_clk_mout_g2d0.clk,
|
||||
[1] = &exynos4x12_clk_mout_g2d1.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
|
||||
.sources = exynos4x12_clkset_mout_g2d_list,
|
||||
.nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
&clk_mout_mpll_user,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
{
|
||||
.clk = {
|
||||
.name = "sclk_fimg2d",
|
||||
},
|
||||
.sources = &exynos4x12_clkset_mout_g2d,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
{
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.9",
|
||||
.enable = exynos4_clk_ip_dmc_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.12",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (7 << 8),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.13",
|
||||
.enable = exynos4212_clk_ip_isp1_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.14",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 11),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.15",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "flite",
|
||||
.devname = "exynos-fimc-lite.0",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "flite",
|
||||
.devname = "exynos-fimc-lite.1",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "fimg2d",
|
||||
.enable = exynos4_clk_ip_dmc_ctrl,
|
||||
.ctrlbit = (1 << 23),
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4212_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4212_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4212_clock_suspend NULL
|
||||
#define exynos4212_clock_resume NULL
|
||||
#endif
|
||||
|
||||
static struct syscore_ops exynos4212_clock_syscore_ops = {
|
||||
.suspend = exynos4212_clock_suspend,
|
||||
.resume = exynos4212_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4212_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
/* usbphy1 is removed */
|
||||
exynos4_clkset_group_list[4] = NULL;
|
||||
|
||||
/* mout_mpll_user is used */
|
||||
exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
|
||||
exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
|
||||
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 12;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4212_clock_syscore_ops);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -25,6 +25,8 @@
|
|||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
|
|
@ -39,7 +41,6 @@
|
|||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
|
@ -65,17 +66,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
|
|||
static void exynos4_map_io(void);
|
||||
static void exynos5_map_io(void);
|
||||
static void exynos5440_map_io(void);
|
||||
static void exynos4_init_clocks(int xtal);
|
||||
static void exynos5_init_clocks(int xtal);
|
||||
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
static int exynos_init(void);
|
||||
|
||||
unsigned long xxti_f = 0, xusbxti_f = 0;
|
||||
|
||||
static struct cpu_table cpu_ids[] __initdata = {
|
||||
{
|
||||
.idcode = EXYNOS4210_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4210,
|
||||
|
|
@ -83,7 +83,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS4212_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4212,
|
||||
|
|
@ -91,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS4412_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4412,
|
||||
|
|
@ -99,7 +97,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS5250_SOC_ID,
|
||||
.idmask = EXYNOS5_SOC_MASK,
|
||||
.map_io = exynos5_map_io,
|
||||
.init_clocks = exynos5_init_clocks,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos5250,
|
||||
}, {
|
||||
|
|
@ -397,43 +394,26 @@ static void __init exynos5_map_io(void)
|
|||
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
|
||||
}
|
||||
|
||||
static void __init exynos4_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
exynos4210_register_clocks();
|
||||
else if (soc_is_exynos4212() || soc_is_exynos4412())
|
||||
exynos4212_register_clocks();
|
||||
|
||||
exynos4_register_clocks();
|
||||
exynos4_setup_clocks();
|
||||
}
|
||||
|
||||
static void __init exynos5440_map_io(void)
|
||||
{
|
||||
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
|
||||
}
|
||||
|
||||
static void __init exynos5_init_clocks(int xtal)
|
||||
void __init exynos_init_time(void)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
/* EXYNOS5440 can support only common clock framework */
|
||||
|
||||
if (soc_is_exynos5440())
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_SOC_EXYNOS5250
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
exynos5_register_clocks();
|
||||
exynos5_setup_clocks();
|
||||
if (of_have_populated_dt()) {
|
||||
#ifdef CONFIG_OF
|
||||
of_clk_init(NULL);
|
||||
clocksource_of_init();
|
||||
#endif
|
||||
} else {
|
||||
/* todo: remove after migrating legacy E4 platforms to dt */
|
||||
#ifdef CONFIG_ARCH_EXYNOS4
|
||||
exynos4_clk_init(NULL);
|
||||
exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
|
||||
#endif
|
||||
mct_init();
|
||||
}
|
||||
}
|
||||
|
||||
void __init exynos4_init_irq(void)
|
||||
|
|
|
|||
|
|
@ -12,7 +12,11 @@
|
|||
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
|
||||
#include <linux/of.h>
|
||||
|
||||
extern void mct_init(void);
|
||||
void exynos_init_time(void);
|
||||
extern unsigned long xxti_f, xusbxti_f;
|
||||
|
||||
struct map_desc;
|
||||
void exynos_init_io(struct map_desc *mach_desc, int size);
|
||||
|
|
@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd);
|
|||
void exynos5_restart(char mode, const char *cmd);
|
||||
void exynos_init_late(void);
|
||||
|
||||
/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
|
||||
void exynos4_clk_init(struct device_node *np);
|
||||
void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS
|
||||
int exynos_pm_late_initcall(void);
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -256,113 +256,6 @@
|
|||
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
|
||||
|
||||
/* For EXYNOS5250 */
|
||||
|
||||
#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
|
||||
#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
|
||||
#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
|
||||
#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
|
||||
#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
|
||||
#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
|
||||
#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
|
||||
#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
|
||||
|
||||
#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
|
||||
#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
|
||||
|
||||
#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
|
||||
#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
|
||||
|
||||
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
|
||||
|
||||
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
|
||||
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
|
||||
#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
|
||||
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
|
||||
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
|
||||
#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
|
||||
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
|
||||
|
||||
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
|
||||
#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
|
||||
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
|
||||
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
|
||||
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
|
||||
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
|
||||
#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
|
||||
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
|
||||
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
|
||||
#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
|
||||
#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
|
||||
|
||||
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
|
||||
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
|
||||
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
|
||||
#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
|
||||
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
|
||||
|
||||
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
|
||||
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
|
||||
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
|
||||
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
|
||||
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
|
||||
#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
|
||||
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
|
||||
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
|
||||
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
|
||||
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
|
||||
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
|
||||
#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
|
||||
#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
|
||||
#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
|
||||
#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
|
||||
#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
|
||||
#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
|
||||
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
|
||||
#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
|
||||
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
|
||||
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
|
||||
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
|
||||
#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
|
||||
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
|
||||
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
|
||||
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
|
||||
#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
|
||||
#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
|
||||
#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
|
||||
|
||||
#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
|
||||
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
|
||||
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
|
||||
|
||||
#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
|
||||
|
||||
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
|
||||
|
||||
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
|
||||
|
||||
#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
|
||||
#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
|
||||
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
|
||||
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
|
||||
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
|
||||
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
|
||||
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
|
||||
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
|
||||
|
||||
#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
|
||||
#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
|
||||
#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
|
||||
#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
|
||||
#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
|
||||
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
|
||||
|
||||
/* Compatibility defines and inclusion */
|
||||
|
||||
#include <mach/regs-pmu.h>
|
||||
|
|
|
|||
|
|
@ -177,7 +177,6 @@ static void __init armlex4210_smsc911x_init(void)
|
|||
static void __init armlex4210_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(armlex4210_uartcfgs,
|
||||
ARRAY_SIZE(armlex4210_uartcfgs));
|
||||
}
|
||||
|
|
@ -202,6 +201,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
|
|||
.map_io = armlex4210_map_io,
|
||||
.init_machine = armlex4210_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = mct_init,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -11,122 +11,26 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/mfc.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The following lookup table is used to override device names when devices
|
||||
* are registered from device tree. This is temporarily added to enable
|
||||
* device tree support addition for the Exynos4 architecture.
|
||||
*
|
||||
* For drivers that require platform data to be provided from the machine
|
||||
* file, a platform data pointer can also be supplied along with the
|
||||
* devices names. Usually, the platform data elements that cannot be parsed
|
||||
* from the device tree by the drivers (example: function pointers) are
|
||||
* supplied. But it should be noted that this is a temporary mechanism and
|
||||
* at some point, the drivers should be capable of parsing all the platform
|
||||
* data from the device tree.
|
||||
*/
|
||||
static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
|
||||
"exynos4210-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
|
||||
"exynos4210-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
|
||||
"exynos4210-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
|
||||
"exynos4-sdhci.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
|
||||
"exynos4-sdhci.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
|
||||
"exynos4-sdhci.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
|
||||
"exynos4-sdhci.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
|
||||
"s3c2440-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
|
||||
"s3c2440-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
|
||||
"s3c2440-i2c.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
|
||||
"s3c2440-i2c.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
|
||||
"s3c2440-i2c.4", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
|
||||
"s3c2440-i2c.5", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
|
||||
"s3c2440-i2c.6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
|
||||
"s3c2440-i2c.7", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
|
||||
"exynos4210-spi.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
|
||||
"exynos4210-spi.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
|
||||
"exynos4210-spi.2", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
|
||||
"exynos-tmu", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
|
||||
"exynos-sysmmu.0", NULL), /* MFC_L */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
|
||||
"exynos-sysmmu.1", NULL), /* MFC_R */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
|
||||
"exynos-sysmmu.2", NULL), /* TV */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
|
||||
"exynos-sysmmu.3", NULL), /* JPEG */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
|
||||
"exynos-sysmmu.4", NULL), /* ROTATOR */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
|
||||
"exynos-sysmmu.5", NULL), /* FIMC0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
|
||||
"exynos-sysmmu.6", NULL), /* FIMC1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
|
||||
"exynos-sysmmu.7", NULL), /* FIMC2 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
|
||||
"exynos-sysmmu.8", NULL), /* FIMC3 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
|
||||
"exynos-sysmmu.9", NULL), /* G2D(4210) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
|
||||
"exynos-sysmmu.9", NULL), /* G2D(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
|
||||
"exynos-sysmmu.10", NULL), /* FIMD0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
|
||||
"exynos-sysmmu.11", NULL), /* FIMD1(4210) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
|
||||
"exynos-sysmmu.12", NULL), /* IS0(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
|
||||
"exynos-sysmmu.13", NULL), /* IS1(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
|
||||
"exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
|
||||
"exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init exynos4_dt_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos4_dt_machine_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos4_auxdata_lookup, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static char const *exynos4_dt_compat[] __initdata = {
|
||||
|
|
@ -136,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static void __init exynos4_reserve(void)
|
||||
{
|
||||
#ifdef CONFIG_S5P_DEV_MFC
|
||||
struct s5p_mfc_dt_meminfo mfc_mem;
|
||||
|
||||
/* Reserve memory for MFC only if it's available */
|
||||
mfc_mem.compatible = "samsung,mfc-v5";
|
||||
if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
|
||||
s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
|
||||
mfc_mem.lsize);
|
||||
#endif
|
||||
}
|
||||
DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
||||
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
|
|
@ -143,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
|||
.map_io = exynos4_dt_map_io,
|
||||
.init_machine = exynos4_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = clocksource_of_init,
|
||||
.init_time = exynos_init_time,
|
||||
.dt_compat = exynos4_dt_compat,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = exynos4_reserve,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -11,152 +11,21 @@
|
|||
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/mfc.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The following lookup table is used to override device names when devices
|
||||
* are registered from device tree. This is temporarily added to enable
|
||||
* device tree support addition for the EXYNOS5 architecture.
|
||||
*
|
||||
* For drivers that require platform data to be provided from the machine
|
||||
* file, a platform data pointer can also be supplied along with the
|
||||
* devices names. Usually, the platform data elements that cannot be parsed
|
||||
* from the device tree by the drivers (example: function pointers) are
|
||||
* supplied. But it should be noted that this is a temporary mechanism and
|
||||
* at some point, the drivers should be capable of parsing all the platform
|
||||
* data from the device tree.
|
||||
*/
|
||||
static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
|
||||
"exynos4210-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
|
||||
"exynos4210-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
|
||||
"exynos4210-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
|
||||
"s3c2440-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
|
||||
"s3c2440-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
|
||||
"s3c2440-i2c.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
|
||||
"s3c2440-i2c.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
|
||||
"s3c2440-i2c.4", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
|
||||
"s3c2440-i2c.5", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
|
||||
"s3c2440-i2c.6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
|
||||
"s3c2440-i2c.7", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
|
||||
"s3c2440-hdmiphy-i2c", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
|
||||
"dw_mmc.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
|
||||
"dw_mmc.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
|
||||
"dw_mmc.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
|
||||
"dw_mmc.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
|
||||
"exynos4210-spi.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
|
||||
"exynos4210-spi.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
|
||||
"exynos4210-spi.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
|
||||
"exynos5-sata", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
|
||||
"exynos5-sata-phy", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
|
||||
"exynos5-sata-phy-i2c", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
|
||||
"exynos-gsc.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
|
||||
"exynos-gsc.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
|
||||
"exynos-gsc.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
|
||||
"exynos-gsc.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
|
||||
"exynos5-hdmi", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
|
||||
"exynos5-mixer", NULL),
|
||||
OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
|
||||
"exynos-tmu", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
|
||||
"samsung-i2s.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
|
||||
"samsung-i2s.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
|
||||
"samsung-i2s.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
|
||||
"exynos-sysmmu.0", "mfc"), /* MFC_L */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
|
||||
"exynos-sysmmu.1", "mfc"), /* MFC_R */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
|
||||
"exynos-sysmmu.2", NULL), /* TV */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
|
||||
"exynos-sysmmu.3", "jpeg"), /* JPEG */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
|
||||
"exynos-sysmmu.4", NULL), /* ROTATOR */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
|
||||
"exynos-sysmmu.5", "gscl"), /* GSCL0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
|
||||
"exynos-sysmmu.6", "gscl"), /* GSCL1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
|
||||
"exynos-sysmmu.7", "gscl"), /* GSCL2 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
|
||||
"exynos-sysmmu.8", "gscl"), /* GSCL3 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
|
||||
"exynos-sysmmu.9", NULL), /* FIMC-IS0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
|
||||
"exynos-sysmmu.10", NULL), /* FIMC-IS1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
|
||||
"exynos-sysmmu.11", NULL), /* FIMD1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
|
||||
"exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
|
||||
"exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
|
||||
"exynos-sysmmu.14", NULL), /* G2D */
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init exynos5_dt_map_io(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
exynos_init_io(NULL, 0);
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos5_dt_machine_init(void)
|
||||
|
|
@ -183,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
|
|||
}
|
||||
}
|
||||
|
||||
if (of_machine_is_compatible("samsung,exynos5250"))
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5250_auxdata_lookup, NULL);
|
||||
else if (of_machine_is_compatible("samsung,exynos5440"))
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5440_auxdata_lookup, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static char const *exynos5_dt_compat[] __initdata = {
|
||||
|
|
@ -217,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
|
|||
.map_io = exynos5_dt_map_io,
|
||||
.init_machine = exynos5_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = clocksource_of_init,
|
||||
.init_time = exynos_init_time,
|
||||
.dt_compat = exynos5_dt_compat,
|
||||
.restart = exynos5_restart,
|
||||
.reserve = exynos5_reserve,
|
||||
|
|
|
|||
|
|
@ -1330,8 +1330,9 @@ static struct platform_device *nuri_devices[] __initdata = {
|
|||
static void __init nuri_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
|
||||
xxti_f = 0;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void __init nuri_reserve(void)
|
||||
|
|
@ -1380,7 +1381,7 @@ MACHINE_START(NURI, "NURI")
|
|||
.map_io = nuri_map_io,
|
||||
.init_machine = nuri_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = mct_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &nuri_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -754,8 +754,9 @@ static void s5p_tv_setup(void)
|
|||
static void __init origen_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
|
||||
xxti_f = 0;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void __init origen_power_init(void)
|
||||
|
|
@ -815,7 +816,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
|
|||
.map_io = origen_map_io,
|
||||
.init_machine = origen_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = mct_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &origen_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -322,7 +322,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
|
|||
static void __init smdk4x12_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
|
||||
}
|
||||
|
||||
|
|
@ -376,7 +375,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
|
|||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdk4x12_map_io,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.init_time = mct_init,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = &smdk4x12_reserve,
|
||||
MACHINE_END
|
||||
|
|
@ -390,7 +389,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
|
|||
.map_io = smdk4x12_map_io,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = mct_init,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = &smdk4x12_reserve,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -371,8 +371,9 @@ static void s5p_tv_setup(void)
|
|||
static void __init smdkv310_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
|
||||
xxti_f = 12000000;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void __init smdkv310_reserve(void)
|
||||
|
|
@ -423,7 +424,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
|
|||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.init_time = mct_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &smdkv310_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -436,7 +437,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
|
|||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = mct_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &smdkv310_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -1092,9 +1092,10 @@ static struct platform_device *universal_devices[] __initdata = {
|
|||
static void __init universal_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
|
||||
xxti_f = 0;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void s5p_tv_setup(void)
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ config PLAT_S5P
|
|||
select PLAT_SAMSUNG
|
||||
select S3C_GPIO_TRACK
|
||||
select S5P_GPIO_DRVSTR
|
||||
select SAMSUNG_CLKSRC
|
||||
select SAMSUNG_CLKSRC if !COMMON_CLK
|
||||
select SAMSUNG_GPIOLIB_4BIT
|
||||
select SAMSUNG_IRQ_VIC_TIMER
|
||||
help
|
||||
|
|
@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC
|
|||
used by newer systems such as the S3C64XX.
|
||||
|
||||
config S5P_CLOCK
|
||||
def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
|
||||
def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
|
||||
help
|
||||
Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_U8500) += ux500/
|
|||
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
|
||||
obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
|
||||
|
||||
obj-$(CONFIG_X86) += x86/
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,8 @@
|
|||
#
|
||||
# Samsung Clock specific Makefile
|
||||
#
|
||||
|
||||
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,523 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2013 Linaro Ltd.
|
||||
* Author: Thomas Abraham <thomas.ab@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Common Clock Framework support for Exynos5250 SoC.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include "clk.h"
|
||||
#include "clk-pll.h"
|
||||
|
||||
#define SRC_CPU 0x200
|
||||
#define DIV_CPU0 0x500
|
||||
#define SRC_CORE1 0x4204
|
||||
#define SRC_TOP0 0x10210
|
||||
#define SRC_TOP2 0x10218
|
||||
#define SRC_GSCL 0x10220
|
||||
#define SRC_DISP1_0 0x1022c
|
||||
#define SRC_MAU 0x10240
|
||||
#define SRC_FSYS 0x10244
|
||||
#define SRC_GEN 0x10248
|
||||
#define SRC_PERIC0 0x10250
|
||||
#define SRC_PERIC1 0x10254
|
||||
#define SRC_MASK_GSCL 0x10320
|
||||
#define SRC_MASK_DISP1_0 0x1032c
|
||||
#define SRC_MASK_MAU 0x10334
|
||||
#define SRC_MASK_FSYS 0x10340
|
||||
#define SRC_MASK_GEN 0x10344
|
||||
#define SRC_MASK_PERIC0 0x10350
|
||||
#define SRC_MASK_PERIC1 0x10354
|
||||
#define DIV_TOP0 0x10510
|
||||
#define DIV_TOP1 0x10514
|
||||
#define DIV_GSCL 0x10520
|
||||
#define DIV_DISP1_0 0x1052c
|
||||
#define DIV_GEN 0x1053c
|
||||
#define DIV_MAU 0x10544
|
||||
#define DIV_FSYS0 0x10548
|
||||
#define DIV_FSYS1 0x1054c
|
||||
#define DIV_FSYS2 0x10550
|
||||
#define DIV_PERIC0 0x10558
|
||||
#define DIV_PERIC1 0x1055c
|
||||
#define DIV_PERIC2 0x10560
|
||||
#define DIV_PERIC3 0x10564
|
||||
#define DIV_PERIC4 0x10568
|
||||
#define DIV_PERIC5 0x1056c
|
||||
#define GATE_IP_GSCL 0x10920
|
||||
#define GATE_IP_MFC 0x1092c
|
||||
#define GATE_IP_GEN 0x10934
|
||||
#define GATE_IP_FSYS 0x10944
|
||||
#define GATE_IP_PERIC 0x10950
|
||||
#define GATE_IP_PERIS 0x10960
|
||||
#define SRC_CDREX 0x20200
|
||||
#define PLL_DIV2_SEL 0x20a24
|
||||
#define GATE_IP_DISP1 0x10928
|
||||
|
||||
/*
|
||||
* Let each supported clock get a unique id. This id is used to lookup the clock
|
||||
* for device tree based platforms. The clocks are categorized into three
|
||||
* sections: core, sclk gate and bus interface gate clocks.
|
||||
*
|
||||
* When adding a new clock to this list, it is advised to choose a clock
|
||||
* category and add it to the end of that category. That is because the the
|
||||
* device tree source file is referring to these ids and any change in the
|
||||
* sequence number of existing clocks will require corresponding change in the
|
||||
* device tree files. This limitation would go away when pre-processor support
|
||||
* for dtc would be available.
|
||||
*/
|
||||
enum exynos5250_clks {
|
||||
none,
|
||||
|
||||
/* core clocks */
|
||||
fin_pll,
|
||||
|
||||
/* gate for special clocks (sclk) */
|
||||
sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
|
||||
sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
|
||||
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
|
||||
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
|
||||
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
|
||||
|
||||
/* gate clocks */
|
||||
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
|
||||
smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
|
||||
jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
|
||||
usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
|
||||
sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
|
||||
i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
|
||||
spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
|
||||
hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
|
||||
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
|
||||
wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
|
||||
|
||||
nr_clks,
|
||||
};
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
*/
|
||||
static __initdata unsigned long exynos5250_clk_regs[] = {
|
||||
SRC_CPU,
|
||||
DIV_CPU0,
|
||||
SRC_CORE1,
|
||||
SRC_TOP0,
|
||||
SRC_TOP2,
|
||||
SRC_GSCL,
|
||||
SRC_DISP1_0,
|
||||
SRC_MAU,
|
||||
SRC_FSYS,
|
||||
SRC_GEN,
|
||||
SRC_PERIC0,
|
||||
SRC_PERIC1,
|
||||
SRC_MASK_GSCL,
|
||||
SRC_MASK_DISP1_0,
|
||||
SRC_MASK_MAU,
|
||||
SRC_MASK_FSYS,
|
||||
SRC_MASK_GEN,
|
||||
SRC_MASK_PERIC0,
|
||||
SRC_MASK_PERIC1,
|
||||
DIV_TOP0,
|
||||
DIV_TOP1,
|
||||
DIV_GSCL,
|
||||
DIV_DISP1_0,
|
||||
DIV_GEN,
|
||||
DIV_MAU,
|
||||
DIV_FSYS0,
|
||||
DIV_FSYS1,
|
||||
DIV_FSYS2,
|
||||
DIV_PERIC0,
|
||||
DIV_PERIC1,
|
||||
DIV_PERIC2,
|
||||
DIV_PERIC3,
|
||||
DIV_PERIC4,
|
||||
DIV_PERIC5,
|
||||
GATE_IP_GSCL,
|
||||
GATE_IP_MFC,
|
||||
GATE_IP_GEN,
|
||||
GATE_IP_FSYS,
|
||||
GATE_IP_PERIC,
|
||||
GATE_IP_PERIS,
|
||||
SRC_CDREX,
|
||||
PLL_DIV2_SEL,
|
||||
GATE_IP_DISP1,
|
||||
};
|
||||
|
||||
/* list of all parent clock list */
|
||||
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
|
||||
PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
|
||||
PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
|
||||
PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
|
||||
PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
|
||||
PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
|
||||
PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
|
||||
PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
|
||||
PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
|
||||
PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
|
||||
PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" };
|
||||
PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" };
|
||||
PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" };
|
||||
PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" };
|
||||
PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
|
||||
PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" };
|
||||
PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
|
||||
"sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
|
||||
"sclk_mpll_user", "sclk_epll", "sclk_vpll",
|
||||
"sclk_cpll" };
|
||||
PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
|
||||
"sclk_uhostphy", "sclk_hdmiphy",
|
||||
"sclk_mpll_user", "sclk_epll", "sclk_vpll",
|
||||
"sclk_cpll" };
|
||||
PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
|
||||
"sclk_uhostphy", "sclk_hdmiphy",
|
||||
"sclk_mpll_user", "sclk_epll", "sclk_vpll",
|
||||
"sclk_cpll" };
|
||||
PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
|
||||
"sclk_uhostphy", "sclk_hdmiphy",
|
||||
"sclk_mpll_user", "sclk_epll", "sclk_vpll",
|
||||
"sclk_cpll" };
|
||||
PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
|
||||
"spdif_extclk" };
|
||||
|
||||
/* fixed rate clocks generated outside the soc */
|
||||
struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
|
||||
FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
|
||||
};
|
||||
|
||||
/* fixed rate clocks generated inside the soc */
|
||||
struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
|
||||
FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
|
||||
FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
|
||||
FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
|
||||
FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
|
||||
};
|
||||
|
||||
struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
|
||||
FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
|
||||
};
|
||||
|
||||
struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
|
||||
MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
|
||||
MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
|
||||
MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
|
||||
MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
|
||||
MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
|
||||
MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
|
||||
MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
|
||||
MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
|
||||
MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
|
||||
MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
|
||||
MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
|
||||
MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
|
||||
MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
|
||||
MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
|
||||
MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
|
||||
MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
|
||||
MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
|
||||
MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
|
||||
MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
|
||||
MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
|
||||
MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
|
||||
MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
|
||||
MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
|
||||
MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
|
||||
MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
|
||||
MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
|
||||
MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
|
||||
MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
|
||||
MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
|
||||
MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
|
||||
MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
|
||||
MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
|
||||
MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
|
||||
MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
|
||||
MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
|
||||
MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
|
||||
MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
|
||||
MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
|
||||
MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
|
||||
MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
|
||||
MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
|
||||
MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
|
||||
MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
|
||||
};
|
||||
|
||||
struct samsung_div_clock exynos5250_div_clks[] __initdata = {
|
||||
DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
|
||||
DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
|
||||
DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
|
||||
DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
|
||||
DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
|
||||
DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
|
||||
DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
|
||||
DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
|
||||
DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
|
||||
DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
|
||||
DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
|
||||
DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
|
||||
DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
|
||||
DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
|
||||
DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
|
||||
DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
|
||||
DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
|
||||
DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
|
||||
DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
|
||||
DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
|
||||
DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
|
||||
DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 8, 8),
|
||||
DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 24, 8),
|
||||
DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 8, 8),
|
||||
DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 24, 8),
|
||||
DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
|
||||
DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
|
||||
DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
|
||||
DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
|
||||
DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
|
||||
DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
|
||||
DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
|
||||
DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
|
||||
DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
|
||||
DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
|
||||
DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
|
||||
DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
|
||||
DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
|
||||
DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
|
||||
DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
|
||||
DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
|
||||
DIV_F(none, "div_mipi1_pre", "div_mipi1",
|
||||
DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_mmc_pre0", "div_mmc0",
|
||||
DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_mmc_pre1", "div_mmc1",
|
||||
DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_mmc_pre2", "div_mmc2",
|
||||
DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_mmc_pre3", "div_mmc3",
|
||||
DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_spi_pre0", "div_spi0",
|
||||
DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_spi_pre1", "div_spi1",
|
||||
DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_spi_pre2", "div_spi2",
|
||||
DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
||||
struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
|
||||
GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
|
||||
GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
|
||||
GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
|
||||
GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
|
||||
GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
|
||||
GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
|
||||
GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
|
||||
GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
|
||||
GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
|
||||
GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
|
||||
GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
|
||||
GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
|
||||
GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
|
||||
GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
|
||||
GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
|
||||
GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
|
||||
GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
|
||||
GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0),
|
||||
GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
|
||||
GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
|
||||
GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
|
||||
GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
|
||||
GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
|
||||
GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
|
||||
GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
|
||||
GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
|
||||
GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
|
||||
GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
|
||||
GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
|
||||
GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
|
||||
GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
|
||||
GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
|
||||
GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
|
||||
GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
|
||||
GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
|
||||
GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
|
||||
GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
|
||||
GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
|
||||
GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
|
||||
GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
|
||||
GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
|
||||
GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
|
||||
GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
|
||||
GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
|
||||
GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
|
||||
GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
|
||||
GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
|
||||
GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
|
||||
GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
|
||||
GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
|
||||
GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
|
||||
GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
|
||||
GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
|
||||
GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
|
||||
GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
|
||||
GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
|
||||
GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
|
||||
GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
|
||||
GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
|
||||
GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
|
||||
GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
|
||||
GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
|
||||
GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
|
||||
GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
|
||||
GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, 0, 0),
|
||||
GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
|
||||
GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
|
||||
GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
|
||||
GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
|
||||
GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
|
||||
GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
|
||||
GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
|
||||
GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
|
||||
GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
|
||||
GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
|
||||
GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
|
||||
GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
|
||||
GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
|
||||
GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
|
||||
GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
|
||||
GATE(cmu_top, "cmu_top", "aclk66",
|
||||
GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(cmu_core, "cmu_core", "aclk66",
|
||||
GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(cmu_mem, "cmu_mem", "aclk66",
|
||||
GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
|
||||
SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_cam0, "sclk_cam0", "div_cam0",
|
||||
SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_cam1, "sclk_cam1", "div_cam1",
|
||||
SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
|
||||
SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
|
||||
SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
|
||||
SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
|
||||
SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_dp, "sclk_dp", "div_dp",
|
||||
SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
|
||||
SRC_MASK_DISP1_0, 20, 0, 0),
|
||||
GATE(sclk_audio0, "sclk_audio0", "div_audio0",
|
||||
SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mmc0, "sclk_mmc0", "div_mmc0",
|
||||
SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mmc1, "sclk_mmc1", "div_mmc1",
|
||||
SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mmc2, "sclk_mmc2", "div_mmc2",
|
||||
SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mmc3, "sclk_mmc3", "div_mmc3",
|
||||
SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_sata, "sclk_sata", "div_sata",
|
||||
SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_usb3, "sclk_usb3", "div_usb3",
|
||||
SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
|
||||
SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart0, "sclk_uart0", "div_uart0",
|
||||
SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart1, "sclk_uart1", "div_uart1",
|
||||
SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart2, "sclk_uart2", "div_uart2",
|
||||
SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart3, "sclk_uart3", "div_uart3",
|
||||
SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_pwm, "sclk_pwm", "div_pwm",
|
||||
SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_audio1, "sclk_audio1", "div_audio1",
|
||||
SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_audio2, "sclk_audio2", "div_audio2",
|
||||
SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
|
||||
SRC_MASK_PERIC1, 4, 0, 0),
|
||||
GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
|
||||
SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
|
||||
SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
|
||||
SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
|
||||
GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
|
||||
GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
|
||||
GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
|
||||
GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
|
||||
GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
|
||||
};
|
||||
|
||||
static __initdata struct of_device_id ext_clk_match[] = {
|
||||
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
|
||||
{ },
|
||||
};
|
||||
|
||||
/* register exynox5250 clocks */
|
||||
void __init exynos5250_clk_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
|
||||
|
||||
if (np) {
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
} else {
|
||||
panic("%s: unable to determine soc\n", __func__);
|
||||
}
|
||||
|
||||
samsung_clk_init(np, reg_base, nr_clks,
|
||||
exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
|
||||
NULL, 0);
|
||||
samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
|
||||
ext_clk_match);
|
||||
|
||||
apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
|
||||
reg_base + 0x100);
|
||||
mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
|
||||
reg_base + 0x4100);
|
||||
bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
|
||||
reg_base + 0x20110);
|
||||
gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
|
||||
reg_base + 0x10150);
|
||||
cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
|
||||
reg_base + 0x10120);
|
||||
epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
|
||||
reg_base + 0x10130);
|
||||
vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
|
||||
reg_base + 0x10140);
|
||||
|
||||
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
|
||||
ARRAY_SIZE(exynos5250_fixed_rate_clks));
|
||||
samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos5250_fixed_factor_clks));
|
||||
samsung_clk_register_mux(exynos5250_mux_clks,
|
||||
ARRAY_SIZE(exynos5250_mux_clks));
|
||||
samsung_clk_register_div(exynos5250_div_clks,
|
||||
ARRAY_SIZE(exynos5250_div_clks));
|
||||
samsung_clk_register_gate(exynos5250_gate_clks,
|
||||
ARRAY_SIZE(exynos5250_gate_clks));
|
||||
|
||||
pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
|
||||
_get_rate("armclk"));
|
||||
}
|
||||
CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Thomas Abraham <thomas.ab@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Common Clock Framework support for Exynos5440 SoC.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include "clk.h"
|
||||
#include "clk-pll.h"
|
||||
|
||||
#define CLKEN_OV_VAL 0xf8
|
||||
#define CPU_CLK_STATUS 0xfc
|
||||
#define MISC_DOUT1 0x558
|
||||
|
||||
/*
|
||||
* Let each supported clock get a unique id. This id is used to lookup the clock
|
||||
* for device tree based platforms.
|
||||
*/
|
||||
enum exynos5440_clks {
|
||||
none, xtal, arm_clk,
|
||||
|
||||
spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
|
||||
usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
|
||||
b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
|
||||
|
||||
nr_clks,
|
||||
};
|
||||
|
||||
/* parent clock name list */
|
||||
PNAME(mout_armclk_p) = { "cplla", "cpllb" };
|
||||
PNAME(mout_spi_p) = { "div125", "div200" };
|
||||
|
||||
/* fixed rate clocks generated outside the soc */
|
||||
struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
|
||||
FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
|
||||
};
|
||||
|
||||
/* fixed rate clocks */
|
||||
struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
|
||||
FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
|
||||
FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
|
||||
FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
|
||||
FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
|
||||
FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
|
||||
};
|
||||
|
||||
/* fixed factor clocks */
|
||||
struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(none, "div250", "ppll", 1, 4, 0),
|
||||
FFACTOR(none, "div200", "ppll", 1, 5, 0),
|
||||
FFACTOR(none, "div125", "div250", 1, 2, 0),
|
||||
};
|
||||
|
||||
/* mux clocks */
|
||||
struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
|
||||
MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
|
||||
MUX_A(arm_clk, "arm_clk", mout_armclk_p,
|
||||
CPU_CLK_STATUS, 0, 1, "armclk"),
|
||||
};
|
||||
|
||||
/* divider clocks */
|
||||
struct samsung_div_clock exynos5440_div_clks[] __initdata = {
|
||||
DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
|
||||
};
|
||||
|
||||
/* gate clocks */
|
||||
struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
|
||||
GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
|
||||
GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
|
||||
GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
|
||||
GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
|
||||
GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
|
||||
GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
|
||||
GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
|
||||
GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
|
||||
GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
|
||||
GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
|
||||
GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
|
||||
GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
|
||||
GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
|
||||
GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
|
||||
GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
|
||||
GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
|
||||
GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
|
||||
GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
|
||||
GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
|
||||
GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
|
||||
};
|
||||
|
||||
static __initdata struct of_device_id ext_clk_match[] = {
|
||||
{ .compatible = "samsung,clock-xtal", .data = (void *)0, },
|
||||
{},
|
||||
};
|
||||
|
||||
/* register exynos5440 clocks */
|
||||
void __init exynos5440_clk_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
pr_err("%s: failed to map clock controller registers,"
|
||||
" aborting clock initialization\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
|
||||
samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
|
||||
|
||||
samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
|
||||
samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
|
||||
|
||||
samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
|
||||
ARRAY_SIZE(exynos5440_fixed_rate_clks));
|
||||
samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos5440_fixed_factor_clks));
|
||||
samsung_clk_register_mux(exynos5440_mux_clks,
|
||||
ARRAY_SIZE(exynos5440_mux_clks));
|
||||
samsung_clk_register_div(exynos5440_div_clks,
|
||||
ARRAY_SIZE(exynos5440_div_clks));
|
||||
samsung_clk_register_gate(exynos5440_gate_clks,
|
||||
ARRAY_SIZE(exynos5440_gate_clks));
|
||||
|
||||
pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk"));
|
||||
pr_info("exynos5440 clock initialization complete\n");
|
||||
}
|
||||
CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
|
||||
|
|
@ -0,0 +1,419 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2013 Linaro Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This file contains the utility functions to register the pll clocks.
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include "clk.h"
|
||||
#include "clk-pll.h"
|
||||
|
||||
/*
|
||||
* PLL35xx Clock Type
|
||||
*/
|
||||
|
||||
#define PLL35XX_MDIV_MASK (0x3FF)
|
||||
#define PLL35XX_PDIV_MASK (0x3F)
|
||||
#define PLL35XX_SDIV_MASK (0x7)
|
||||
#define PLL35XX_MDIV_SHIFT (16)
|
||||
#define PLL35XX_PDIV_SHIFT (8)
|
||||
#define PLL35XX_SDIV_SHIFT (0)
|
||||
|
||||
struct samsung_clk_pll35xx {
|
||||
struct clk_hw hw;
|
||||
const void __iomem *con_reg;
|
||||
};
|
||||
|
||||
#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
|
||||
|
||||
static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
|
||||
u32 mdiv, pdiv, sdiv, pll_con;
|
||||
u64 fvco = parent_rate;
|
||||
|
||||
pll_con = __raw_readl(pll->con_reg);
|
||||
mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
|
||||
pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
|
||||
sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
|
||||
|
||||
fvco *= mdiv;
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
|
||||
return (unsigned long)fvco;
|
||||
}
|
||||
|
||||
static const struct clk_ops samsung_pll35xx_clk_ops = {
|
||||
.recalc_rate = samsung_pll35xx_recalc_rate,
|
||||
};
|
||||
|
||||
struct clk * __init samsung_clk_register_pll35xx(const char *name,
|
||||
const char *pname, const void __iomem *con_reg)
|
||||
{
|
||||
struct samsung_clk_pll35xx *pll;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll) {
|
||||
pr_err("%s: could not allocate pll clk %s\n", __func__, name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.ops = &samsung_pll35xx_clk_ops;
|
||||
init.flags = CLK_GET_RATE_NOCACHE;
|
||||
init.parent_names = &pname;
|
||||
init.num_parents = 1;
|
||||
|
||||
pll->hw.init = &init;
|
||||
pll->con_reg = con_reg;
|
||||
|
||||
clk = clk_register(NULL, &pll->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register pll clock %s\n", __func__,
|
||||
name);
|
||||
kfree(pll);
|
||||
}
|
||||
|
||||
if (clk_register_clkdev(clk, name, NULL))
|
||||
pr_err("%s: failed to register lookup for %s", __func__, name);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/*
|
||||
* PLL36xx Clock Type
|
||||
*/
|
||||
|
||||
#define PLL36XX_KDIV_MASK (0xFFFF)
|
||||
#define PLL36XX_MDIV_MASK (0x1FF)
|
||||
#define PLL36XX_PDIV_MASK (0x3F)
|
||||
#define PLL36XX_SDIV_MASK (0x7)
|
||||
#define PLL36XX_MDIV_SHIFT (16)
|
||||
#define PLL36XX_PDIV_SHIFT (8)
|
||||
#define PLL36XX_SDIV_SHIFT (0)
|
||||
|
||||
struct samsung_clk_pll36xx {
|
||||
struct clk_hw hw;
|
||||
const void __iomem *con_reg;
|
||||
};
|
||||
|
||||
#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
|
||||
|
||||
static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
|
||||
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
|
||||
u64 fvco = parent_rate;
|
||||
|
||||
pll_con0 = __raw_readl(pll->con_reg);
|
||||
pll_con1 = __raw_readl(pll->con_reg + 4);
|
||||
mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
|
||||
kdiv = pll_con1 & PLL36XX_KDIV_MASK;
|
||||
|
||||
fvco *= (mdiv << 16) + kdiv;
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
fvco >>= 16;
|
||||
|
||||
return (unsigned long)fvco;
|
||||
}
|
||||
|
||||
static const struct clk_ops samsung_pll36xx_clk_ops = {
|
||||
.recalc_rate = samsung_pll36xx_recalc_rate,
|
||||
};
|
||||
|
||||
struct clk * __init samsung_clk_register_pll36xx(const char *name,
|
||||
const char *pname, const void __iomem *con_reg)
|
||||
{
|
||||
struct samsung_clk_pll36xx *pll;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll) {
|
||||
pr_err("%s: could not allocate pll clk %s\n", __func__, name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.ops = &samsung_pll36xx_clk_ops;
|
||||
init.flags = CLK_GET_RATE_NOCACHE;
|
||||
init.parent_names = &pname;
|
||||
init.num_parents = 1;
|
||||
|
||||
pll->hw.init = &init;
|
||||
pll->con_reg = con_reg;
|
||||
|
||||
clk = clk_register(NULL, &pll->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register pll clock %s\n", __func__,
|
||||
name);
|
||||
kfree(pll);
|
||||
}
|
||||
|
||||
if (clk_register_clkdev(clk, name, NULL))
|
||||
pr_err("%s: failed to register lookup for %s", __func__, name);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/*
|
||||
* PLL45xx Clock Type
|
||||
*/
|
||||
|
||||
#define PLL45XX_MDIV_MASK (0x3FF)
|
||||
#define PLL45XX_PDIV_MASK (0x3F)
|
||||
#define PLL45XX_SDIV_MASK (0x7)
|
||||
#define PLL45XX_MDIV_SHIFT (16)
|
||||
#define PLL45XX_PDIV_SHIFT (8)
|
||||
#define PLL45XX_SDIV_SHIFT (0)
|
||||
|
||||
struct samsung_clk_pll45xx {
|
||||
struct clk_hw hw;
|
||||
enum pll45xx_type type;
|
||||
const void __iomem *con_reg;
|
||||
};
|
||||
|
||||
#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
|
||||
|
||||
static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
|
||||
u32 mdiv, pdiv, sdiv, pll_con;
|
||||
u64 fvco = parent_rate;
|
||||
|
||||
pll_con = __raw_readl(pll->con_reg);
|
||||
mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
|
||||
pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
|
||||
sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
|
||||
|
||||
if (pll->type == pll_4508)
|
||||
sdiv = sdiv - 1;
|
||||
|
||||
fvco *= mdiv;
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
|
||||
return (unsigned long)fvco;
|
||||
}
|
||||
|
||||
static const struct clk_ops samsung_pll45xx_clk_ops = {
|
||||
.recalc_rate = samsung_pll45xx_recalc_rate,
|
||||
};
|
||||
|
||||
struct clk * __init samsung_clk_register_pll45xx(const char *name,
|
||||
const char *pname, const void __iomem *con_reg,
|
||||
enum pll45xx_type type)
|
||||
{
|
||||
struct samsung_clk_pll45xx *pll;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll) {
|
||||
pr_err("%s: could not allocate pll clk %s\n", __func__, name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.ops = &samsung_pll45xx_clk_ops;
|
||||
init.flags = CLK_GET_RATE_NOCACHE;
|
||||
init.parent_names = &pname;
|
||||
init.num_parents = 1;
|
||||
|
||||
pll->hw.init = &init;
|
||||
pll->con_reg = con_reg;
|
||||
pll->type = type;
|
||||
|
||||
clk = clk_register(NULL, &pll->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register pll clock %s\n", __func__,
|
||||
name);
|
||||
kfree(pll);
|
||||
}
|
||||
|
||||
if (clk_register_clkdev(clk, name, NULL))
|
||||
pr_err("%s: failed to register lookup for %s", __func__, name);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/*
|
||||
* PLL46xx Clock Type
|
||||
*/
|
||||
|
||||
#define PLL46XX_MDIV_MASK (0x1FF)
|
||||
#define PLL46XX_PDIV_MASK (0x3F)
|
||||
#define PLL46XX_SDIV_MASK (0x7)
|
||||
#define PLL46XX_MDIV_SHIFT (16)
|
||||
#define PLL46XX_PDIV_SHIFT (8)
|
||||
#define PLL46XX_SDIV_SHIFT (0)
|
||||
|
||||
#define PLL46XX_KDIV_MASK (0xFFFF)
|
||||
#define PLL4650C_KDIV_MASK (0xFFF)
|
||||
#define PLL46XX_KDIV_SHIFT (0)
|
||||
|
||||
struct samsung_clk_pll46xx {
|
||||
struct clk_hw hw;
|
||||
enum pll46xx_type type;
|
||||
const void __iomem *con_reg;
|
||||
};
|
||||
|
||||
#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw)
|
||||
|
||||
static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw);
|
||||
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
|
||||
u64 fvco = parent_rate;
|
||||
|
||||
pll_con0 = __raw_readl(pll->con_reg);
|
||||
pll_con1 = __raw_readl(pll->con_reg + 4);
|
||||
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
|
||||
kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
|
||||
pll_con1 & PLL46XX_KDIV_MASK;
|
||||
|
||||
shift = pll->type == pll_4600 ? 16 : 10;
|
||||
fvco *= (mdiv << shift) + kdiv;
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
fvco >>= shift;
|
||||
|
||||
return (unsigned long)fvco;
|
||||
}
|
||||
|
||||
static const struct clk_ops samsung_pll46xx_clk_ops = {
|
||||
.recalc_rate = samsung_pll46xx_recalc_rate,
|
||||
};
|
||||
|
||||
struct clk * __init samsung_clk_register_pll46xx(const char *name,
|
||||
const char *pname, const void __iomem *con_reg,
|
||||
enum pll46xx_type type)
|
||||
{
|
||||
struct samsung_clk_pll46xx *pll;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll) {
|
||||
pr_err("%s: could not allocate pll clk %s\n", __func__, name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.ops = &samsung_pll46xx_clk_ops;
|
||||
init.flags = CLK_GET_RATE_NOCACHE;
|
||||
init.parent_names = &pname;
|
||||
init.num_parents = 1;
|
||||
|
||||
pll->hw.init = &init;
|
||||
pll->con_reg = con_reg;
|
||||
pll->type = type;
|
||||
|
||||
clk = clk_register(NULL, &pll->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register pll clock %s\n", __func__,
|
||||
name);
|
||||
kfree(pll);
|
||||
}
|
||||
|
||||
if (clk_register_clkdev(clk, name, NULL))
|
||||
pr_err("%s: failed to register lookup for %s", __func__, name);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/*
|
||||
* PLL2550x Clock Type
|
||||
*/
|
||||
|
||||
#define PLL2550X_R_MASK (0x1)
|
||||
#define PLL2550X_P_MASK (0x3F)
|
||||
#define PLL2550X_M_MASK (0x3FF)
|
||||
#define PLL2550X_S_MASK (0x7)
|
||||
#define PLL2550X_R_SHIFT (20)
|
||||
#define PLL2550X_P_SHIFT (14)
|
||||
#define PLL2550X_M_SHIFT (4)
|
||||
#define PLL2550X_S_SHIFT (0)
|
||||
|
||||
struct samsung_clk_pll2550x {
|
||||
struct clk_hw hw;
|
||||
const void __iomem *reg_base;
|
||||
unsigned long offset;
|
||||
};
|
||||
|
||||
#define to_clk_pll2550x(_hw) container_of(_hw, struct samsung_clk_pll2550x, hw)
|
||||
|
||||
static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw);
|
||||
u32 r, p, m, s, pll_stat;
|
||||
u64 fvco = parent_rate;
|
||||
|
||||
pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
|
||||
r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
|
||||
if (!r)
|
||||
return 0;
|
||||
p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
|
||||
m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
|
||||
s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
|
||||
|
||||
fvco *= m;
|
||||
do_div(fvco, (p << s));
|
||||
|
||||
return (unsigned long)fvco;
|
||||
}
|
||||
|
||||
static const struct clk_ops samsung_pll2550x_clk_ops = {
|
||||
.recalc_rate = samsung_pll2550x_recalc_rate,
|
||||
};
|
||||
|
||||
struct clk * __init samsung_clk_register_pll2550x(const char *name,
|
||||
const char *pname, const void __iomem *reg_base,
|
||||
const unsigned long offset)
|
||||
{
|
||||
struct samsung_clk_pll2550x *pll;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll) {
|
||||
pr_err("%s: could not allocate pll clk %s\n", __func__, name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.ops = &samsung_pll2550x_clk_ops;
|
||||
init.flags = CLK_GET_RATE_NOCACHE;
|
||||
init.parent_names = &pname;
|
||||
init.num_parents = 1;
|
||||
|
||||
pll->hw.init = &init;
|
||||
pll->reg_base = reg_base;
|
||||
pll->offset = offset;
|
||||
|
||||
clk = clk_register(NULL, &pll->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register pll clock %s\n", __func__,
|
||||
name);
|
||||
kfree(pll);
|
||||
}
|
||||
|
||||
if (clk_register_clkdev(clk, name, NULL))
|
||||
pr_err("%s: failed to register lookup for %s", __func__, name);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2013 Linaro Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Common Clock Framework support for all PLL's in Samsung platforms
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_CLK_PLL_H
|
||||
#define __SAMSUNG_CLK_PLL_H
|
||||
|
||||
enum pll45xx_type {
|
||||
pll_4500,
|
||||
pll_4502,
|
||||
pll_4508
|
||||
};
|
||||
|
||||
enum pll46xx_type {
|
||||
pll_4600,
|
||||
pll_4650,
|
||||
pll_4650c,
|
||||
};
|
||||
|
||||
extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
|
||||
const char *pname, const void __iomem *con_reg);
|
||||
extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
|
||||
const char *pname, const void __iomem *con_reg);
|
||||
extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
|
||||
const char *pname, const void __iomem *con_reg,
|
||||
enum pll45xx_type type);
|
||||
extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
|
||||
const char *pname, const void __iomem *con_reg,
|
||||
enum pll46xx_type type);
|
||||
extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
|
||||
const char *pname, const void __iomem *reg_base,
|
||||
const unsigned long offset);
|
||||
|
||||
#endif /* __SAMSUNG_CLK_PLL_H */
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2013 Linaro Ltd.
|
||||
* Author: Thomas Abraham <thomas.ab@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This file includes utility functions to register clocks to common
|
||||
* clock framework for Samsung platforms.
|
||||
*/
|
||||
|
||||
#include <linux/syscore_ops.h>
|
||||
#include "clk.h"
|
||||
|
||||
static DEFINE_SPINLOCK(lock);
|
||||
static struct clk **clk_table;
|
||||
static void __iomem *reg_base;
|
||||
#ifdef CONFIG_OF
|
||||
static struct clk_onecell_data clk_data;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *reg_dump;
|
||||
static unsigned long nr_reg_dump;
|
||||
|
||||
static int samsung_clk_suspend(void)
|
||||
{
|
||||
struct samsung_clk_reg_dump *rd = reg_dump;
|
||||
unsigned long i;
|
||||
|
||||
for (i = 0; i < nr_reg_dump; i++, rd++)
|
||||
rd->value = __raw_readl(reg_base + rd->offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void samsung_clk_resume(void)
|
||||
{
|
||||
struct samsung_clk_reg_dump *rd = reg_dump;
|
||||
unsigned long i;
|
||||
|
||||
for (i = 0; i < nr_reg_dump; i++, rd++)
|
||||
__raw_writel(rd->value, reg_base + rd->offset);
|
||||
}
|
||||
|
||||
static struct syscore_ops samsung_clk_syscore_ops = {
|
||||
.suspend = samsung_clk_suspend,
|
||||
.resume = samsung_clk_resume,
|
||||
};
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
/* setup the essentials required to support clock lookup using ccf */
|
||||
void __init samsung_clk_init(struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks, unsigned long *rdump,
|
||||
unsigned long nr_rdump, unsigned long *soc_rdump,
|
||||
unsigned long nr_soc_rdump)
|
||||
{
|
||||
reg_base = base;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
if (rdump && nr_rdump) {
|
||||
unsigned int idx;
|
||||
reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
|
||||
* (nr_rdump + nr_soc_rdump), GFP_KERNEL);
|
||||
if (!reg_dump) {
|
||||
pr_err("%s: memory alloc for register dump failed\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
for (idx = 0; idx < nr_rdump; idx++)
|
||||
reg_dump[idx].offset = rdump[idx];
|
||||
for (idx = 0; idx < nr_soc_rdump; idx++)
|
||||
reg_dump[nr_rdump + idx].offset = soc_rdump[idx];
|
||||
nr_reg_dump = nr_rdump + nr_soc_rdump;
|
||||
register_syscore_ops(&samsung_clk_syscore_ops);
|
||||
}
|
||||
#endif
|
||||
|
||||
clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
|
||||
if (!clk_table)
|
||||
panic("could not allocate clock lookup table\n");
|
||||
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
clk_data.clks = clk_table;
|
||||
clk_data.clk_num = nr_clks;
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* add a clock instance to the clock lookup table used for dt based lookup */
|
||||
void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
|
||||
{
|
||||
if (clk_table && id)
|
||||
clk_table[id] = clk;
|
||||
}
|
||||
|
||||
/* register a list of aliases */
|
||||
void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
|
||||
unsigned int nr_clk)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned int idx, ret;
|
||||
|
||||
if (!clk_table) {
|
||||
pr_err("%s: clock table missing\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
if (!list->id) {
|
||||
pr_err("%s: clock id missing for index %d\n", __func__,
|
||||
idx);
|
||||
continue;
|
||||
}
|
||||
|
||||
clk = clk_table[list->id];
|
||||
if (!clk) {
|
||||
pr_err("%s: failed to find clock %d\n", __func__,
|
||||
list->id);
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = clk_register_clkdev(clk, list->alias, list->dev_name);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register lookup %s\n",
|
||||
__func__, list->alias);
|
||||
}
|
||||
}
|
||||
|
||||
/* register a list of fixed clocks */
|
||||
void __init samsung_clk_register_fixed_rate(
|
||||
struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned int idx, ret;
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
clk = clk_register_fixed_rate(NULL, list->name,
|
||||
list->parent_name, list->flags, list->fixed_rate);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
list->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
samsung_clk_add_lookup(clk, list->id);
|
||||
|
||||
/*
|
||||
* Unconditionally add a clock lookup for the fixed rate clocks.
|
||||
* There are not many of these on any of Samsung platforms.
|
||||
*/
|
||||
ret = clk_register_clkdev(clk, list->name, NULL);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register clock lookup for %s",
|
||||
__func__, list->name);
|
||||
}
|
||||
}
|
||||
|
||||
/* register a list of fixed factor clocks */
|
||||
void __init samsung_clk_register_fixed_factor(
|
||||
struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned int idx;
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
clk = clk_register_fixed_factor(NULL, list->name,
|
||||
list->parent_name, list->flags, list->mult, list->div);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
list->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
samsung_clk_add_lookup(clk, list->id);
|
||||
}
|
||||
}
|
||||
|
||||
/* register a list of mux clocks */
|
||||
void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
|
||||
unsigned int nr_clk)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned int idx, ret;
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
clk = clk_register_mux(NULL, list->name, list->parent_names,
|
||||
list->num_parents, list->flags, reg_base + list->offset,
|
||||
list->shift, list->width, list->mux_flags, &lock);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
list->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
samsung_clk_add_lookup(clk, list->id);
|
||||
|
||||
/* register a clock lookup only if a clock alias is specified */
|
||||
if (list->alias) {
|
||||
ret = clk_register_clkdev(clk, list->alias,
|
||||
list->dev_name);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register lookup %s\n",
|
||||
__func__, list->alias);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* register a list of div clocks */
|
||||
void __init samsung_clk_register_div(struct samsung_div_clock *list,
|
||||
unsigned int nr_clk)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned int idx, ret;
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
if (list->table)
|
||||
clk = clk_register_divider_table(NULL, list->name,
|
||||
list->parent_name, list->flags,
|
||||
reg_base + list->offset, list->shift,
|
||||
list->width, list->div_flags,
|
||||
list->table, &lock);
|
||||
else
|
||||
clk = clk_register_divider(NULL, list->name,
|
||||
list->parent_name, list->flags,
|
||||
reg_base + list->offset, list->shift,
|
||||
list->width, list->div_flags, &lock);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
list->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
samsung_clk_add_lookup(clk, list->id);
|
||||
|
||||
/* register a clock lookup only if a clock alias is specified */
|
||||
if (list->alias) {
|
||||
ret = clk_register_clkdev(clk, list->alias,
|
||||
list->dev_name);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register lookup %s\n",
|
||||
__func__, list->alias);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* register a list of gate clocks */
|
||||
void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
|
||||
unsigned int nr_clk)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned int idx, ret;
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
clk = clk_register_gate(NULL, list->name, list->parent_name,
|
||||
list->flags, reg_base + list->offset,
|
||||
list->bit_idx, list->gate_flags, &lock);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
list->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* register a clock lookup only if a clock alias is specified */
|
||||
if (list->alias) {
|
||||
ret = clk_register_clkdev(clk, list->alias,
|
||||
list->dev_name);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register lookup %s\n",
|
||||
__func__, list->alias);
|
||||
}
|
||||
|
||||
samsung_clk_add_lookup(clk, list->id);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* obtain the clock speed of all external fixed clock sources from device
|
||||
* tree and register it
|
||||
*/
|
||||
#ifdef CONFIG_OF
|
||||
void __init samsung_clk_of_register_fixed_ext(
|
||||
struct samsung_fixed_rate_clock *fixed_rate_clk,
|
||||
unsigned int nr_fixed_rate_clk,
|
||||
struct of_device_id *clk_matches)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct device_node *np;
|
||||
u32 freq;
|
||||
|
||||
for_each_matching_node_and_match(np, clk_matches, &match) {
|
||||
if (of_property_read_u32(np, "clock-frequency", &freq))
|
||||
continue;
|
||||
fixed_rate_clk[(u32)match->data].fixed_rate = freq;
|
||||
}
|
||||
samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* utility function to get the rate of a specified clock */
|
||||
unsigned long _get_rate(const char *clk_name)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned long rate;
|
||||
|
||||
clk = clk_get(NULL, clk_name);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: could not find clock %s\n", __func__, clk_name);
|
||||
return 0;
|
||||
}
|
||||
rate = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
return rate;
|
||||
}
|
||||
|
|
@ -0,0 +1,289 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2013 Linaro Ltd.
|
||||
* Author: Thomas Abraham <thomas.ab@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Common Clock Framework support for all Samsung platforms
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_CLK_H
|
||||
#define __SAMSUNG_CLK_H
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
/**
|
||||
* struct samsung_clock_alias: information about mux clock
|
||||
* @id: platform specific id of the clock.
|
||||
* @dev_name: name of the device to which this clock belongs.
|
||||
* @alias: optional clock alias name to be assigned to this clock.
|
||||
*/
|
||||
struct samsung_clock_alias {
|
||||
unsigned int id;
|
||||
const char *dev_name;
|
||||
const char *alias;
|
||||
};
|
||||
|
||||
#define ALIAS(_id, dname, a) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.dev_name = dname, \
|
||||
.alias = a, \
|
||||
}
|
||||
|
||||
/**
|
||||
* struct samsung_fixed_rate_clock: information about fixed-rate clock
|
||||
* @id: platform specific id of the clock.
|
||||
* @name: name of this fixed-rate clock.
|
||||
* @parent_name: optional parent clock name.
|
||||
* @flags: optional fixed-rate clock flags.
|
||||
* @fixed-rate: fixed clock rate of this clock.
|
||||
*/
|
||||
struct samsung_fixed_rate_clock {
|
||||
unsigned int id;
|
||||
char *name;
|
||||
const char *parent_name;
|
||||
unsigned long flags;
|
||||
unsigned long fixed_rate;
|
||||
};
|
||||
|
||||
#define FRATE(_id, cname, pname, f, frate) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = cname, \
|
||||
.parent_name = pname, \
|
||||
.flags = f, \
|
||||
.fixed_rate = frate, \
|
||||
}
|
||||
|
||||
/*
|
||||
* struct samsung_fixed_factor_clock: information about fixed-factor clock
|
||||
* @id: platform specific id of the clock.
|
||||
* @name: name of this fixed-factor clock.
|
||||
* @parent_name: parent clock name.
|
||||
* @mult: fixed multiplication factor.
|
||||
* @div: fixed division factor.
|
||||
* @flags: optional fixed-factor clock flags.
|
||||
*/
|
||||
struct samsung_fixed_factor_clock {
|
||||
unsigned int id;
|
||||
char *name;
|
||||
const char *parent_name;
|
||||
unsigned long mult;
|
||||
unsigned long div;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
#define FFACTOR(_id, cname, pname, m, d, f) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = cname, \
|
||||
.parent_name = pname, \
|
||||
.mult = m, \
|
||||
.div = d, \
|
||||
.flags = f, \
|
||||
}
|
||||
|
||||
/**
|
||||
* struct samsung_mux_clock: information about mux clock
|
||||
* @id: platform specific id of the clock.
|
||||
* @dev_name: name of the device to which this clock belongs.
|
||||
* @name: name of this mux clock.
|
||||
* @parent_names: array of pointer to parent clock names.
|
||||
* @num_parents: number of parents listed in @parent_names.
|
||||
* @flags: optional flags for basic clock.
|
||||
* @offset: offset of the register for configuring the mux.
|
||||
* @shift: starting bit location of the mux control bit-field in @reg.
|
||||
* @width: width of the mux control bit-field in @reg.
|
||||
* @mux_flags: flags for mux-type clock.
|
||||
* @alias: optional clock alias name to be assigned to this clock.
|
||||
*/
|
||||
struct samsung_mux_clock {
|
||||
unsigned int id;
|
||||
const char *dev_name;
|
||||
const char *name;
|
||||
const char **parent_names;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 mux_flags;
|
||||
const char *alias;
|
||||
};
|
||||
|
||||
#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.dev_name = dname, \
|
||||
.name = cname, \
|
||||
.parent_names = pnames, \
|
||||
.num_parents = ARRAY_SIZE(pnames), \
|
||||
.flags = f, \
|
||||
.offset = o, \
|
||||
.shift = s, \
|
||||
.width = w, \
|
||||
.mux_flags = mf, \
|
||||
.alias = a, \
|
||||
}
|
||||
|
||||
#define MUX(_id, cname, pnames, o, s, w) \
|
||||
__MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
|
||||
|
||||
#define MUX_A(_id, cname, pnames, o, s, w, a) \
|
||||
__MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
|
||||
|
||||
#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
|
||||
__MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
|
||||
|
||||
/**
|
||||
* @id: platform specific id of the clock.
|
||||
* struct samsung_div_clock: information about div clock
|
||||
* @dev_name: name of the device to which this clock belongs.
|
||||
* @name: name of this div clock.
|
||||
* @parent_name: name of the parent clock.
|
||||
* @flags: optional flags for basic clock.
|
||||
* @offset: offset of the register for configuring the div.
|
||||
* @shift: starting bit location of the div control bit-field in @reg.
|
||||
* @div_flags: flags for div-type clock.
|
||||
* @alias: optional clock alias name to be assigned to this clock.
|
||||
*/
|
||||
struct samsung_div_clock {
|
||||
unsigned int id;
|
||||
const char *dev_name;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 div_flags;
|
||||
const char *alias;
|
||||
struct clk_div_table *table;
|
||||
};
|
||||
|
||||
#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.dev_name = dname, \
|
||||
.name = cname, \
|
||||
.parent_name = pname, \
|
||||
.flags = f, \
|
||||
.offset = o, \
|
||||
.shift = s, \
|
||||
.width = w, \
|
||||
.div_flags = df, \
|
||||
.alias = a, \
|
||||
.table = t, \
|
||||
}
|
||||
|
||||
#define DIV(_id, cname, pname, o, s, w) \
|
||||
__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
|
||||
|
||||
#define DIV_A(_id, cname, pname, o, s, w, a) \
|
||||
__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
|
||||
|
||||
#define DIV_F(_id, cname, pname, o, s, w, f, df) \
|
||||
__DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
|
||||
|
||||
#define DIV_T(_id, cname, pname, o, s, w, t) \
|
||||
__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
|
||||
|
||||
/**
|
||||
* struct samsung_gate_clock: information about gate clock
|
||||
* @id: platform specific id of the clock.
|
||||
* @dev_name: name of the device to which this clock belongs.
|
||||
* @name: name of this gate clock.
|
||||
* @parent_name: name of the parent clock.
|
||||
* @flags: optional flags for basic clock.
|
||||
* @offset: offset of the register for configuring the gate.
|
||||
* @bit_idx: bit index of the gate control bit-field in @reg.
|
||||
* @gate_flags: flags for gate-type clock.
|
||||
* @alias: optional clock alias name to be assigned to this clock.
|
||||
*/
|
||||
struct samsung_gate_clock {
|
||||
unsigned int id;
|
||||
const char *dev_name;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
u8 bit_idx;
|
||||
u8 gate_flags;
|
||||
const char *alias;
|
||||
};
|
||||
|
||||
#define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.dev_name = dname, \
|
||||
.name = cname, \
|
||||
.parent_name = pname, \
|
||||
.flags = f, \
|
||||
.offset = o, \
|
||||
.bit_idx = b, \
|
||||
.gate_flags = gf, \
|
||||
.alias = a, \
|
||||
}
|
||||
|
||||
#define GATE(_id, cname, pname, o, b, f, gf) \
|
||||
__GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
|
||||
|
||||
#define GATE_A(_id, cname, pname, o, b, f, gf, a) \
|
||||
__GATE(_id, NULL, cname, pname, o, b, f, gf, a)
|
||||
|
||||
#define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
|
||||
__GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
|
||||
|
||||
#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
|
||||
__GATE(_id, dname, cname, pname, o, b, f, gf, a)
|
||||
|
||||
#define PNAME(x) static const char *x[] __initdata
|
||||
|
||||
/**
|
||||
* struct samsung_clk_reg_dump: register dump of clock controller registers.
|
||||
* @offset: clock register offset from the controller base address.
|
||||
* @value: the value to be register at offset.
|
||||
*/
|
||||
struct samsung_clk_reg_dump {
|
||||
u32 offset;
|
||||
u32 value;
|
||||
};
|
||||
|
||||
extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks, unsigned long *rdump,
|
||||
unsigned long nr_rdump, unsigned long *soc_rdump,
|
||||
unsigned long nr_soc_rdump);
|
||||
extern void __init samsung_clk_of_register_fixed_ext(
|
||||
struct samsung_fixed_rate_clock *fixed_rate_clk,
|
||||
unsigned int nr_fixed_rate_clk,
|
||||
struct of_device_id *clk_matches);
|
||||
|
||||
extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
|
||||
|
||||
extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
|
||||
unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_fixed_rate(
|
||||
struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_fixed_factor(
|
||||
struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
|
||||
unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
|
||||
unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_gate(
|
||||
struct samsung_gate_clock *clk_list, unsigned int nr_clk);
|
||||
|
||||
extern unsigned long _get_rate(const char *clk_name);
|
||||
|
||||
#endif /* __SAMSUNG_CLK_H */
|
||||
|
|
@ -477,12 +477,20 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
|
|||
};
|
||||
#endif /* CONFIG_LOCAL_TIMERS */
|
||||
|
||||
static void __init exynos4_timer_resources(void __iomem *base)
|
||||
static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
|
||||
{
|
||||
struct clk *mct_clk;
|
||||
mct_clk = clk_get(NULL, "xtal");
|
||||
struct clk *mct_clk, *tick_clk;
|
||||
|
||||
clk_rate = clk_get_rate(mct_clk);
|
||||
tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
|
||||
clk_get(NULL, "fin_pll");
|
||||
if (IS_ERR(tick_clk))
|
||||
panic("%s: unable to determine tick clock rate\n", __func__);
|
||||
clk_rate = clk_get_rate(tick_clk);
|
||||
|
||||
mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
|
||||
if (IS_ERR(mct_clk))
|
||||
panic("%s: unable to retrieve mct clock instance\n", __func__);
|
||||
clk_prepare_enable(mct_clk);
|
||||
|
||||
reg_base = base;
|
||||
if (!reg_base)
|
||||
|
|
@ -514,7 +522,7 @@ void __init mct_init(void)
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panic("unable to determine mct controller type\n");
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}
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exynos4_timer_resources(S5P_VA_SYSTIMER);
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||||
exynos4_timer_resources(NULL, S5P_VA_SYSTIMER);
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exynos4_clocksource_init();
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exynos4_clockevent_init();
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}
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|
@ -537,7 +545,7 @@ static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
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for (i = MCT_L0_IRQ; i < nr_irqs; i++)
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||||
mct_irqs[i] = irq_of_parse_and_map(np, i);
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||||
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||||
exynos4_timer_resources(of_iomap(np, 0));
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||||
exynos4_timer_resources(np, of_iomap(np, 0));
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||||
exynos4_clocksource_init();
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||||
exynos4_clockevent_init();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue