From 0880fb86608acf1bbf4df9b3580e5a1b58fe8ba6 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Thu, 23 Aug 2018 15:17:41 +0200 Subject: [PATCH 1/4] clk: ingenic: Add proper Kconfig entries Previously, the CGU code corresponding to the SoC for which we're compiling the kernel was the only one enabled, which made it impossible to build one kernel that supports them all. Now, it is possible to select more than one SoC to support. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 2 +- drivers/clk/ingenic/Kconfig | 37 ++++++++++++++++++++++++++++++++++++ drivers/clk/ingenic/Makefile | 8 ++++---- 4 files changed, 43 insertions(+), 5 deletions(-) create mode 100644 drivers/clk/ingenic/Kconfig diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 292056bbb30e..cd9b1d0cb23b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -287,6 +287,7 @@ source "drivers/clk/actions/Kconfig" source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" +source "drivers/clk/ingenic/Kconfig" source "drivers/clk/keystone/Kconfig" source "drivers/clk/mediatek/Kconfig" source "drivers/clk/meson/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index a84c5573cabe..b3bdcd1c15c4 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -72,7 +72,7 @@ obj-$(CONFIG_H8300) += h8300/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-y += imgtec/ obj-$(CONFIG_ARCH_MXC) += imx/ -obj-$(CONFIG_MACH_INGENIC) += ingenic/ +obj-y += ingenic/ obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ obj-$(CONFIG_MACH_LOONGSON32) += loongson1/ obj-y += mediatek/ diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig new file mode 100644 index 000000000000..2445437f8286 --- /dev/null +++ b/drivers/clk/ingenic/Kconfig @@ -0,0 +1,37 @@ +menu "Ingenic JZ47xx CGU drivers" + depends on MIPS + +config INGENIC_CGU_COMMON + bool + +config INGENIC_CGU_JZ4740 + bool "Ingenic JZ4740 CGU driver" + default MACH_JZ4740 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4740 + and compatible SoCs. + + If building for a JZ4740 SoC, you want to say Y here. + +config INGENIC_CGU_JZ4770 + bool "Ingenic JZ4770 CGU driver" + default MACH_JZ4770 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4770 + and compatible SoCs. + + If building for a JZ4770 SoC, you want to say Y here. + +config INGENIC_CGU_JZ4780 + bool "Ingenic JZ4780 CGU driver" + default MACH_JZ4780 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4780 + and compatible SoCs. + + If building for a JZ4780 SoC, you want to say Y here. + +endmenu diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index 1456e4cdb562..8b8dc79c7ce6 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -1,4 +1,4 @@ -obj-y += cgu.o -obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o -obj-$(CONFIG_MACH_JZ4770) += jz4770-cgu.o -obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o +obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o From 067b6dedeb34ffda811ebbadf8bbad9311f28dc4 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Thu, 23 Aug 2018 15:17:42 +0200 Subject: [PATCH 2/4] dt-bindings: clock: ingenic: Explicitly list compatible strings This is better than letting the other developers wondering what are the supported strings. Signed-off-by: Paul Cercueil Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/ingenic,cgu.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt index f8d4134ae409..ba5a442026b7 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt @@ -6,8 +6,11 @@ to provide many different clock signals derived from only 2 external source clocks. Required properties: -- compatible : Should be "ingenic,-cgu". - For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu". +- compatible : Should be one of: + * ingenic,jz4740-cgu + * ingenic,jz4725b-cgu + * ingenic,jz4770-cgu + * ingenic,jz4780-cgu - reg : The address & length of the CGU registers. - clocks : List of phandle & clock specifiers for clocks external to the CGU. Two such external clocks should be specified - first the external crystal From 2fdecde7752be5696c0ae301a0d1b1884081a0f1 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Thu, 23 Aug 2018 15:17:43 +0200 Subject: [PATCH 3/4] dt-bindings: clock: Add jz4725b-cgu.h header This will be used from the devicetree bindings to specify the clocks that should be obtained from the jz4725b-cgu driver. Signed-off-by: Paul Cercueil Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- include/dt-bindings/clock/jz4725b-cgu.h | 35 +++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 include/dt-bindings/clock/jz4725b-cgu.h diff --git a/include/dt-bindings/clock/jz4725b-cgu.h b/include/dt-bindings/clock/jz4725b-cgu.h new file mode 100644 index 000000000000..460bbeff6ab8 --- /dev/null +++ b/include/dt-bindings/clock/jz4725b-cgu.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ + +#define JZ4725B_CLK_EXT 0 +#define JZ4725B_CLK_OSC32K 1 +#define JZ4725B_CLK_PLL 2 +#define JZ4725B_CLK_PLL_HALF 3 +#define JZ4725B_CLK_CCLK 4 +#define JZ4725B_CLK_HCLK 5 +#define JZ4725B_CLK_PCLK 6 +#define JZ4725B_CLK_MCLK 7 +#define JZ4725B_CLK_IPU 8 +#define JZ4725B_CLK_LCD 9 +#define JZ4725B_CLK_I2S 10 +#define JZ4725B_CLK_SPI 11 +#define JZ4725B_CLK_MMC_MUX 12 +#define JZ4725B_CLK_UDC 13 +#define JZ4725B_CLK_UART 14 +#define JZ4725B_CLK_DMA 15 +#define JZ4725B_CLK_ADC 16 +#define JZ4725B_CLK_I2C 17 +#define JZ4725B_CLK_AIC 18 +#define JZ4725B_CLK_MMC0 19 +#define JZ4725B_CLK_MMC1 20 +#define JZ4725B_CLK_BCH 21 +#define JZ4725B_CLK_TCU 22 +#define JZ4725B_CLK_EXT512 23 +#define JZ4725B_CLK_RTC 24 + +#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */ From 226dfa4726ebb102479d668e01160a1dc77485e8 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Thu, 23 Aug 2018 15:17:44 +0200 Subject: [PATCH 4/4] clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd --- drivers/clk/ingenic/Kconfig | 10 ++ drivers/clk/ingenic/Makefile | 1 + drivers/clk/ingenic/jz4725b-cgu.c | 225 ++++++++++++++++++++++++++++++ 3 files changed, 236 insertions(+) create mode 100644 drivers/clk/ingenic/jz4725b-cgu.c diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index 2445437f8286..34dc0da79c39 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -14,6 +14,16 @@ config INGENIC_CGU_JZ4740 If building for a JZ4740 SoC, you want to say Y here. +config INGENIC_CGU_JZ4725B + bool "Ingenic JZ4725B CGU driver" + default MACH_JZ4725B + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4725B + and compatible SoCs. + + If building for a JZ4725B SoC, you want to say Y here. + config INGENIC_CGU_JZ4770 bool "Ingenic JZ4770 CGU driver" default MACH_JZ4770 diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index 8b8dc79c7ce6..00a79b2fba10 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c new file mode 100644 index 000000000000..584ff4ff81c7 --- /dev/null +++ b/drivers/clk/ingenic/jz4725b-cgu.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Ingenic JZ4725B SoC CGU driver + * + * Copyright (C) 2018 Paul Cercueil + * Author: Paul Cercueil + */ + +#include +#include +#include +#include +#include "cgu.h" + +/* CGU register offsets */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_LCR 0x04 +#define CGU_REG_CPPCR 0x10 +#define CGU_REG_CLKGR 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSCCDR 0x68 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x78 + +/* bits within the LCR register */ +#define LCR_SLEEP BIT(0) + +static struct ingenic_cgu *cgu; + +static const s8 pll_od_encoding[4] = { + 0x0, 0x1, -1, 0x3, +}; + +static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { + + /* External clocks */ + + [JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT }, + [JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, + + [JZ4725B_CLK_PLL] = { + "pll", CGU_CLK_PLL, + .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_CPPCR, + .m_shift = 23, + .m_bits = 9, + .m_offset = 2, + .n_shift = 18, + .n_bits = 5, + .n_offset = 2, + .od_shift = 16, + .od_bits = 2, + .od_max = 4, + .od_encoding = pll_od_encoding, + .stable_bit = 10, + .bypass_bit = 9, + .enable_bit = 8, + }, + }, + + /* Muxes & dividers */ + + [JZ4725B_CLK_PLL_HALF] = { + "pll half", CGU_CLK_DIV, + .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 }, + }, + + [JZ4725B_CLK_CCLK] = { + "cclk", CGU_CLK_DIV, + .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, + }, + + [JZ4725B_CLK_HCLK] = { + "hclk", CGU_CLK_DIV, + .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, + }, + + [JZ4725B_CLK_PCLK] = { + "pclk", CGU_CLK_DIV, + .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 }, + }, + + [JZ4725B_CLK_MCLK] = { + "mclk", CGU_CLK_DIV, + .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 }, + }, + + [JZ4725B_CLK_IPU] = { + "ipu", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 }, + .gate = { CGU_REG_CLKGR, 13 }, + }, + + [JZ4725B_CLK_LCD] = { + "lcd", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 9 }, + }, + + [JZ4725B_CLK_I2S] = { + "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 }, + .mux = { CGU_REG_CPCCR, 31, 1 }, + .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 6 }, + }, + + [JZ4725B_CLK_SPI] = { + "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 }, + .mux = { CGU_REG_SSICDR, 31, 1 }, + .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 4 }, + }, + + [JZ4725B_CLK_MMC_MUX] = { + "mmc_mux", CGU_CLK_DIV, + .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, + }, + + [JZ4725B_CLK_UDC] = { + "udc", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 }, + .mux = { CGU_REG_CPCCR, 29, 1 }, + .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, + }, + + /* Gate-only clocks */ + + [JZ4725B_CLK_UART] = { + "uart", CGU_CLK_GATE, + .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 0 }, + }, + + [JZ4725B_CLK_DMA] = { + "dma", CGU_CLK_GATE, + .parents = { JZ4725B_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 12 }, + }, + + [JZ4725B_CLK_ADC] = { + "adc", CGU_CLK_GATE, + .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 7 }, + }, + + [JZ4725B_CLK_I2C] = { + "i2c", CGU_CLK_GATE, + .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 3 }, + }, + + [JZ4725B_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 5 }, + }, + + [JZ4725B_CLK_MMC0] = { + "mmc0", CGU_CLK_GATE, + .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 6 }, + }, + + [JZ4725B_CLK_MMC1] = { + "mmc1", CGU_CLK_GATE, + .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 16 }, + }, + + [JZ4725B_CLK_BCH] = { + "bch", CGU_CLK_GATE, + .parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + + [JZ4725B_CLK_TCU] = { + "tcu", CGU_CLK_GATE, + .parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 1 }, + }, + + [JZ4725B_CLK_EXT512] = { + "ext/512", CGU_CLK_FIXDIV, + .parents = { JZ4725B_CLK_EXT }, + + /* Doc calls it EXT512, but it seems to be /256... */ + .fixdiv = { 256 }, + }, + + [JZ4725B_CLK_RTC] = { + "rtc", CGU_CLK_MUX, + .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 }, + .mux = { CGU_REG_OPCR, 2, 1}, + }, +}; + +static void __init jz4725b_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(jz4725b_cgu_clocks, + ARRAY_SIZE(jz4725b_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); +} +CLK_OF_DECLARE(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);