ARM: proc-*.S: place cpu_reset functions into .idmap.text section
The CPU reset functions disable the MMU and therefore must be executed with an identity mapping in place. This patch places the CPU reset functions into the .idmap.text section, causing the idmap code to include them as part of the identity mapping. Acked-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>hifive-unleashed-5.1
Will Deacon
parent
e6eadc6787
commit
1a4baafa7d
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@ -95,6 +95,7 @@ ENTRY(cpu_arm1020_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm1020_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -107,6 +108,8 @@ ENTRY(cpu_arm1020_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm1020_reset)
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.popsection
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/*
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* cpu_arm1020_do_idle()
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@ -95,6 +95,7 @@ ENTRY(cpu_arm1020e_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm1020e_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -107,6 +108,8 @@ ENTRY(cpu_arm1020e_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm1020e_reset)
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.popsection
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/*
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* cpu_arm1020e_do_idle()
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@ -84,6 +84,7 @@ ENTRY(cpu_arm1022_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm1022_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -96,6 +97,8 @@ ENTRY(cpu_arm1022_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm1022_reset)
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.popsection
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/*
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* cpu_arm1022_do_idle()
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@ -84,6 +84,7 @@ ENTRY(cpu_arm1026_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm1026_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -96,6 +97,8 @@ ENTRY(cpu_arm1026_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm1026_reset)
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.popsection
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/*
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* cpu_arm1026_do_idle()
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@ -225,6 +225,7 @@ ENTRY(cpu_arm7_set_pte_ext)
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm6_reset)
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ENTRY(cpu_arm7_reset)
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mov r1, #0
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@ -235,6 +236,9 @@ ENTRY(cpu_arm7_reset)
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mov r1, #0x30
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mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
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mov pc, r0
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ENDPROC(cpu_arm6_reset)
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ENDPROC(cpu_arm7_reset)
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.popsection
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__CPUINIT
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@ -101,6 +101,7 @@ ENTRY(cpu_arm720_set_pte_ext)
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm720_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
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@ -112,6 +113,8 @@ ENTRY(cpu_arm720_reset)
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bic ip, ip, #0x2100 @ ..v....s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm720_reset)
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.popsection
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__CPUINIT
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@ -49,6 +49,7 @@ ENTRY(cpu_arm740_proc_fin)
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm740_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
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@ -56,6 +57,8 @@ ENTRY(cpu_arm740_reset)
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bic ip, ip, #0x0000000c @ ............wc..
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm740_reset)
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.popsection
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__CPUINIT
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@ -45,8 +45,11 @@ ENTRY(cpu_arm7tdmi_proc_fin)
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* Params : loc(r0) address to jump to
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* Purpose : Sets up everything for a reset and jump to the location for soft reset.
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*/
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm7tdmi_reset)
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mov pc, r0
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ENDPROC(cpu_arm7tdmi_reset)
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.popsection
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__CPUINIT
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@ -85,6 +85,7 @@ ENTRY(cpu_arm920_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm920_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -97,6 +98,8 @@ ENTRY(cpu_arm920_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm920_reset)
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.popsection
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/*
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* cpu_arm920_do_idle()
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@ -87,6 +87,7 @@ ENTRY(cpu_arm922_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm922_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -99,6 +100,8 @@ ENTRY(cpu_arm922_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm922_reset)
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.popsection
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/*
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* cpu_arm922_do_idle()
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@ -108,6 +108,7 @@ ENTRY(cpu_arm925_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm925_reset)
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/* Send software reset to MPU and DSP */
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mov ip, #0xff000000
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@ -115,6 +116,8 @@ ENTRY(cpu_arm925_reset)
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orr ip, ip, #0x0000ce00
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mov r4, #1
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strh r4, [ip, #0x10]
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ENDPROC(cpu_arm925_reset)
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.popsection
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -77,6 +77,7 @@ ENTRY(cpu_arm926_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm926_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -89,6 +90,8 @@ ENTRY(cpu_arm926_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm926_reset)
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.popsection
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/*
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* cpu_arm926_do_idle()
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@ -48,6 +48,7 @@ ENTRY(cpu_arm940_proc_fin)
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm940_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ flush I cache
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@ -58,6 +59,8 @@ ENTRY(cpu_arm940_reset)
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bic ip, ip, #0x00001000 @ i-cache
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm940_reset)
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.popsection
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/*
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* cpu_arm940_do_idle()
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@ -55,6 +55,7 @@ ENTRY(cpu_arm946_proc_fin)
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm946_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ flush I cache
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@ -65,6 +66,8 @@ ENTRY(cpu_arm946_reset)
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bic ip, ip, #0x00001000 @ i-cache
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm946_reset)
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.popsection
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/*
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* cpu_arm946_do_idle()
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@ -45,8 +45,11 @@ ENTRY(cpu_arm9tdmi_proc_fin)
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* Params : loc(r0) address to jump to
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* Purpose : Sets up everything for a reset and jump to the location for soft reset.
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*/
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm9tdmi_reset)
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mov pc, r0
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ENDPROC(cpu_arm9tdmi_reset)
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.popsection
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__CPUINIT
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@ -57,6 +57,7 @@ ENTRY(cpu_fa526_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 4
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_fa526_reset)
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/* TODO: Use CP8 if possible... */
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mov ip, #0
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@ -73,6 +74,8 @@ ENTRY(cpu_fa526_reset)
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nop
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nop
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mov pc, r0
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ENDPROC(cpu_fa526_reset)
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.popsection
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/*
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* cpu_fa526_do_idle()
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@ -98,6 +98,7 @@ ENTRY(cpu_feroceon_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_feroceon_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -110,6 +111,8 @@ ENTRY(cpu_feroceon_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_feroceon_reset)
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.popsection
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/*
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* cpu_feroceon_do_idle()
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@ -69,6 +69,7 @@ ENTRY(cpu_mohawk_proc_fin)
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* (same as arm926)
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_mohawk_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -79,6 +80,8 @@ ENTRY(cpu_mohawk_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_mohawk_reset)
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.popsection
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/*
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* cpu_mohawk_do_idle()
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@ -62,6 +62,7 @@ ENTRY(cpu_sa110_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_sa110_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -74,6 +75,8 @@ ENTRY(cpu_sa110_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_sa110_reset)
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.popsection
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/*
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* cpu_sa110_do_idle(type)
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@ -70,6 +70,7 @@ ENTRY(cpu_sa1100_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_sa1100_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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@ -82,6 +83,8 @@ ENTRY(cpu_sa1100_reset)
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_sa1100_reset)
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.popsection
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/*
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* cpu_sa1100_do_idle(type)
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@ -55,6 +55,7 @@ ENTRY(cpu_v6_proc_fin)
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* - loc - location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_v6_reset)
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mrc p15, 0, r1, c1, c0, 0 @ ctrl register
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bic r1, r1, #0x1 @ ...............m
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@ -62,6 +63,8 @@ ENTRY(cpu_v6_reset)
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mov r1, #0
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mcr p15, 0, r1, c7, c5, 4 @ ISB
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mov pc, r0
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ENDPROC(cpu_v6_reset)
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.popsection
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/*
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* cpu_v6_do_idle()
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@ -63,6 +63,7 @@ ENDPROC(cpu_v7_proc_fin)
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* caches disabled.
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_v7_reset)
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mrc p15, 0, r1, c1, c0, 0 @ ctrl register
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bic r1, r1, #0x1 @ ...............m
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@ -71,6 +72,7 @@ ENTRY(cpu_v7_reset)
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isb
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mov pc, r0
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ENDPROC(cpu_v7_reset)
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.popsection
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/*
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* cpu_v7_do_idle()
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@ -105,6 +105,7 @@ ENTRY(cpu_xsc3_proc_fin)
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_xsc3_reset)
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mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r1 @ reset CPSR
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@ -119,6 +120,8 @@ ENTRY(cpu_xsc3_reset)
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@ already containing those two last instructions to survive.
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
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mov pc, r0
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ENDPROC(cpu_xsc3_reset)
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.popsection
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/*
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* cpu_xsc3_do_idle()
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@ -142,6 +142,7 @@ ENTRY(cpu_xscale_proc_fin)
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* Beware PXA270 erratum E7.
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_xscale_reset)
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mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r1 @ reset CPSR
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@ -160,6 +161,8 @@ ENTRY(cpu_xscale_reset)
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@ already containing those two last instructions to survive.
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mov pc, r0
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ENDPROC(cpu_xscale_reset)
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.popsection
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/*
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* cpu_xscale_do_idle()
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||||
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|||
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Reference in New Issue