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clk: tegra: fix SS control on PLL enable/disable 

PLL SS was only controlled when setting the PLL rate, not when the PLL itself
is enabled or disabled.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
hifive-unleashed-5.1
Peter De Schrijver 2017-07-25 13:34:02 +03:00 committed by Stephen Boyd
parent de2245540e
commit 1a7da87727
1 changed files with 24 additions and 20 deletions
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44
drivers/clk/tegra/clk-pll.c
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@ -418,6 +418,26 @@ static void _clk_pll_disable(struct clk_hw *hw)
}
}
static void pll_clk_start_ss(struct tegra_clk_pll *pll)
{
if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
val |= pll->params->ssc_ctrl_en_mask;
pll_writel(val, pll->params->ssc_ctrl_reg, pll);
}
}
static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
{
if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
val &= ~pll->params->ssc_ctrl_en_mask;
pll_writel(val, pll->params->ssc_ctrl_reg, pll);
}
}
static int clk_pll_enable(struct clk_hw *hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
@ -431,6 +451,8 @@ static int clk_pll_enable(struct clk_hw *hw)
ret = clk_pll_wait_for_lock(pll);
pll_clk_start_ss(pll);
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
@ -445,6 +467,8 @@ static void clk_pll_disable(struct clk_hw *hw)
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
pll_clk_stop_ss(pll);
_clk_pll_disable(hw);
if (pll->lock)
@ -716,26 +740,6 @@ static void _update_pll_cpcon(struct tegra_clk_pll *pll,
pll_writel_misc(val, pll);
}
static void pll_clk_start_ss(struct tegra_clk_pll *pll)
{
if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
val |= pll->params->ssc_ctrl_en_mask;
pll_writel(val, pll->params->ssc_ctrl_reg, pll);
}
}
static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
{
if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
val &= ~pll->params->ssc_ctrl_en_mask;
pll_writel(val, pll->params->ssc_ctrl_reg, pll);
}
}
static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
unsigned long rate)
{