clk: xgene: Add PMD clock
Add X-Gene PMD clock support. PMD clock is implemented for a single register field. Output rate = parent_rate * (denominator - scale) / denominator with - denominator = bitmask of register field + 1 - scale = values of register field For example, for bitmask is 0x7, denominator will be 8 and scale will be computed and programmed accordingly. Signed-off-by: Hoan Tran <hotran@apm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>hifive-unleashed-5.1
Hoan Tran
Stephen Boyd
parent
405f27be61
commit
1a85b50bef
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@ -217,6 +217,226 @@ static void xgene_pcppllclk_init(struct device_node *np)
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xgene_pllclk_init(np, PLL_TYPE_PCP);
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}
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/**
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* struct xgene_clk_pmd - PMD clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register containing the fractional scale multiplier (scaler)
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* @shift: shift to the unit bit field
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* @denom: 1/denominator unit
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* @lock: register lock
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* Flags:
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* XGENE_CLK_PMD_SCALE_INVERTED - By default the scaler is the value read
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* from the register plus one. For example,
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* 0 for (0 + 1) / denom,
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* 1 for (1 + 1) / denom and etc.
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* If this flag is set, it is
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* 0 for (denom - 0) / denom,
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* 1 for (denom - 1) / denom and etc.
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*
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*/
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struct xgene_clk_pmd {
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struct clk_hw hw;
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void __iomem *reg;
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u8 shift;
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u32 mask;
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u64 denom;
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u32 flags;
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spinlock_t *lock;
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};
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#define to_xgene_clk_pmd(_hw) container_of(_hw, struct xgene_clk_pmd, hw)
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#define XGENE_CLK_PMD_SCALE_INVERTED BIT(0)
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#define XGENE_CLK_PMD_SHIFT 8
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#define XGENE_CLK_PMD_WIDTH 3
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static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw);
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unsigned long flags = 0;
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u64 ret, scale;
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u32 val;
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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else
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__acquire(fd->lock);
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val = clk_readl(fd->reg);
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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else
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__release(fd->lock);
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ret = (u64)parent_rate;
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scale = (val & fd->mask) >> fd->shift;
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if (fd->flags & XGENE_CLK_PMD_SCALE_INVERTED)
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scale = fd->denom - scale;
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else
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scale++;
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/* freq = parent_rate * scaler / denom */
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do_div(ret, fd->denom);
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ret *= scale;
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if (ret == 0)
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ret = (u64)parent_rate;
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return ret;
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}
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static long xgene_clk_pmd_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw);
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u64 ret, scale;
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if (!rate || rate >= *parent_rate)
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return *parent_rate;
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/* freq = parent_rate * scaler / denom */
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ret = rate * fd->denom;
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scale = DIV_ROUND_UP_ULL(ret, *parent_rate);
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ret = (u64)*parent_rate * scale;
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do_div(ret, fd->denom);
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return ret;
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}
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static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw);
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unsigned long flags = 0;
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u64 scale, ret;
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u32 val;
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/*
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* Compute the scaler:
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*
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* freq = parent_rate * scaler / denom, or
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* scaler = freq * denom / parent_rate
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*/
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ret = rate * fd->denom;
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scale = DIV_ROUND_UP_ULL(ret, (u64)parent_rate);
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/* Check if inverted */
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if (fd->flags & XGENE_CLK_PMD_SCALE_INVERTED)
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scale = fd->denom - scale;
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else
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scale--;
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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else
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__acquire(fd->lock);
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val = clk_readl(fd->reg);
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val &= ~fd->mask;
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val |= (scale << fd->shift);
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clk_writel(val, fd->reg);
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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else
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__release(fd->lock);
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return 0;
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}
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static const struct clk_ops xgene_clk_pmd_ops = {
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.recalc_rate = xgene_clk_pmd_recalc_rate,
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.round_rate = xgene_clk_pmd_round_rate,
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.set_rate = xgene_clk_pmd_set_rate,
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};
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static struct clk *
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xgene_register_clk_pmd(struct device *dev,
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const char *name, const char *parent_name,
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unsigned long flags, void __iomem *reg, u8 shift,
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u8 width, u64 denom, u32 clk_flags, spinlock_t *lock)
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{
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struct xgene_clk_pmd *fd;
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struct clk_init_data init;
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struct clk *clk;
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fd = kzalloc(sizeof(*fd), GFP_KERNEL);
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if (!fd)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &xgene_clk_pmd_ops;
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init.flags = flags;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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fd->reg = reg;
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fd->shift = shift;
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fd->mask = (BIT(width) - 1) << shift;
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fd->denom = denom;
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fd->flags = clk_flags;
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fd->lock = lock;
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fd->hw.init = &init;
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clk = clk_register(dev, &fd->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: could not register clk %s\n", __func__, name);
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kfree(fd);
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return NULL;
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}
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return clk;
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}
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static void xgene_pmdclk_init(struct device_node *np)
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{
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const char *clk_name = np->full_name;
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void __iomem *csr_reg;
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struct resource res;
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struct clk *clk;
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u64 denom;
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u32 flags = 0;
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int rc;
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/* Check if the entry is disabled */
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if (!of_device_is_available(np))
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return;
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/* Parse the DTS register for resource */
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rc = of_address_to_resource(np, 0, &res);
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if (rc != 0) {
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pr_err("no DTS register for %s\n", np->full_name);
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return;
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}
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csr_reg = of_iomap(np, 0);
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if (!csr_reg) {
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pr_err("Unable to map resource for %s\n", np->full_name);
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return;
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}
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of_property_read_string(np, "clock-output-names", &clk_name);
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denom = BIT(XGENE_CLK_PMD_WIDTH);
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flags |= XGENE_CLK_PMD_SCALE_INVERTED;
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clk = xgene_register_clk_pmd(NULL, clk_name,
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of_clk_get_parent_name(np, 0), 0,
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csr_reg, XGENE_CLK_PMD_SHIFT,
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XGENE_CLK_PMD_WIDTH, denom,
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flags, &clk_lock);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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pr_debug("Add %s clock\n", clk_name);
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} else {
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if (csr_reg)
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iounmap(csr_reg);
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}
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}
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/* IP Clock */
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struct xgene_dev_parameters {
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void __iomem *csr_reg; /* CSR for IP clock */
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@ -543,6 +763,7 @@ err:
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CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
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CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
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CLK_OF_DECLARE(xgene_pmd_clock, "apm,xgene-pmd-clock", xgene_pmdclk_init);
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CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock",
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xgene_socpllclk_init);
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CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock",
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