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Merge branches 'pm-avs', 'pm-clk' and 'powercap'

* pm-avs:
  PM / AVS: rockchip-io: Fix module autoload for OF platform driver

* pm-clk:
  PM / clk: Fix broken build due to non-matching code and header #ifdefs

* powercap:
  powercap / RAPL: Enable Broxton RAPL support
hifive-unleashed-5.1
Rafael J. Wysocki 2015-11-02 00:54:49 +01:00
commit 1ab68460b1
3 changed files with 5 additions and 3 deletions

View File

@ -17,7 +17,7 @@
#include <linux/err.h>
#include <linux/pm_runtime.h>
#ifdef CONFIG_PM
#ifdef CONFIG_PM_CLK
enum pce_status {
PCE_STATUS_NONE = 0,
@ -404,7 +404,7 @@ int pm_clk_runtime_resume(struct device *dev)
return pm_generic_runtime_resume(dev);
}
#else /* !CONFIG_PM */
#else /* !CONFIG_PM_CLK */
/**
* enable_clock - Enable a device clock.
@ -484,7 +484,7 @@ static int pm_clk_notify(struct notifier_block *nb,
return 0;
}
#endif /* !CONFIG_PM */
#endif /* !CONFIG_PM_CLK */
/**
* pm_clk_add_notifier - Add bus type notifier for power management clocks.

View File

@ -271,6 +271,7 @@ static const struct of_device_id rockchip_iodomain_match[] = {
},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, rockchip_iodomain_match);
static int rockchip_iodomain_probe(struct platform_device *pdev)
{

View File

@ -1102,6 +1102,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
RAPL_CPU(0x4A, rapl_defaults_tng),/* Tangier */
RAPL_CPU(0x56, rapl_defaults_core),/* Future Xeon */
RAPL_CPU(0x5A, rapl_defaults_ann),/* Annidale */
RAPL_CPU(0X5C, rapl_defaults_core),/* Broxton */
RAPL_CPU(0x5E, rapl_defaults_core),/* Skylake-H/S */
RAPL_CPU(0x57, rapl_defaults_hsw_server),/* Knights Landing */
{}