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serial:ifx6x60:SPI header is decoded incorrectly 

This patch is to correct the bit mapping of "MORE" and "CTS" in SPI frame header.
Per SPI protocol, SPI header is encoded with length of 4 byte, which is defined
as below:
bit 0 ~ 11: current data size;
bit 12: "MORE" bit;
bit 13: reserve
bit 14 ~ 15: reserve
bit 16 ~ 27: next data size
bit 28: RI
bit 29: DCD
bit 30: CTS/RTS
bit 31: DSR/DTR

According to above SPI header structure, the bit mapping of "MORE" and "CTS" is
incorrect in function ifx_spi_decode_spi_header();

Cc: Chen Jun <jun.d.chen@intel.com>
Signed-off-by: channing <chao.bi@intel.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
hifive-unleashed-5.1
chao bi 2012-11-06 11:13:59 +08:00 committed by Greg Kroah-Hartman
parent 54d5f88f25
commit 1b2f8a9550
1 changed files with 2 additions and 2 deletions
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4
drivers/tty/serial/ifx6x60.c
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@ -64,8 +64,8 @@
#include "ifx6x60.h"
#define IFX_SPI_MORE_MASK 0x10
#define IFX_SPI_MORE_BIT 12 /* bit position in u16 */
#define IFX_SPI_CTS_BIT 13 /* bit position in u16 */
#define IFX_SPI_MORE_BIT 4 /* bit position in u8 */
#define IFX_SPI_CTS_BIT 6 /* bit position in u8 */
#define IFX_SPI_MODE SPI_MODE_1
#define IFX_SPI_TTY_ID 0
#define IFX_SPI_TIMEOUT_SEC 2