PCI: cadence: Add host driver for Cadence PCIe controller
This patch adds support to the Cadence PCIe controller in host mode. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>hifive-unleashed-5.1
Cyrille Pitchen
Lorenzo Pieralisi
parent
2040fae4b2
commit
1b79c52844
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@ -10402,6 +10402,13 @@ S: Maintained
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F: Documentation/devicetree/bindings/pci/pci-armada8k.txt
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F: drivers/pci/dwc/pcie-armada8k.c
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PCI DRIVER FOR CADENCE PCIE IP
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M: Alan Douglas <adouglas@cadence.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/cdns,*.txt
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F: drivers/pci/host/pcie-cadence*
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PCI DRIVER FOR FREESCALE LAYERSCAPE
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M: Minghuan Lian <minghuan.Lian@freescale.com>
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M: Mingkai Hu <mingkai.hu@freescale.com>
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@ -210,6 +210,16 @@ config PCIE_TANGO_SMP8759
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This can lead to data corruption if drivers perform concurrent
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config and MMIO accesses.
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config PCIE_CADENCE_HOST
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bool "Cadence PCIe host controller"
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depends on OF
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depends on PCI
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select IRQ_DOMAIN
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help
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Say Y here if you want to support the Cadence PCIe controller in host
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mode. This PCIe controller may be embedded into many different vendors
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SoCs.
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config VMD
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depends on PCI_MSI && X86_64 && SRCU
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tristate "Intel Volume Management Device Driver"
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@ -22,6 +22,7 @@ obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
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obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
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obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
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obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
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obj-$(CONFIG_VMD) += vmd.o
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# The following drivers are for devices that use the generic ACPI
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@ -0,0 +1,397 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2017 Cadence
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// Cadence PCIe host controller driver.
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// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "pcie-cadence.h"
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/**
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* struct cdns_pcie_rc - private data for this PCIe Root Complex driver
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* @pcie: Cadence PCIe controller
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* @dev: pointer to PCIe device
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* @cfg_res: start/end offsets in the physical system memory to map PCI
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* configuration space accesses
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* @bus_range: first/last buses behind the PCIe host controller
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* @cfg_base: IO mapped window to access the PCI configuration space of a
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* single function at a time
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* @max_regions: maximum number of regions supported by the hardware
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* @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
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* translation (nbits sets into the "no BAR match" register)
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* @vendor_id: PCI vendor ID
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* @device_id: PCI device ID
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*/
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struct cdns_pcie_rc {
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struct cdns_pcie pcie;
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struct device *dev;
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struct resource *cfg_res;
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struct resource *bus_range;
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void __iomem *cfg_base;
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u32 max_regions;
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u32 no_bar_nbits;
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u16 vendor_id;
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u16 device_id;
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};
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static void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie,
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u32 r, bool is_io,
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u64 cpu_addr, u64 pci_addr, size_t size)
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{
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/*
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* roundup_pow_of_two() returns an unsigned long, which is not suited
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* for 64bit values.
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*/
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u64 sz = 1ULL << fls64(size - 1);
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int nbits = ilog2(sz);
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u32 addr0, addr1, desc0, desc1;
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if (nbits < 8)
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nbits = 8;
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/* Set the PCI address */
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addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) |
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(lower_32_bits(pci_addr) & GENMASK(31, 8));
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addr1 = upper_32_bits(pci_addr);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1);
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/* Set the PCIe header descriptor */
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if (is_io)
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desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO;
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else
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desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM;
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desc1 = 0;
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/*
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* Whatever Bit [23] is set or not inside DESC0 register of the outbound
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* PCIe descriptor, the PCI function number must be set into
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* Bits [26:24] of DESC0 anyway.
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*
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* In Root Complex mode, the function number is always 0 but in Endpoint
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* mode, the PCIe controller may support more than one function. This
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* function number needs to be set properly into the outbound PCIe
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* descriptor.
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*
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* Besides, setting Bit [23] is mandatory when in Root Complex mode:
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* then the driver must provide the bus, resp. device, number in
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* Bits [7:0] of DESC1, resp. Bits[31:27] of DESC0. Like the function
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* number, the device number is always 0 in Root Complex mode.
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*/
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
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CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
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desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(pcie->bus);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
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/* Set the CPU address */
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cpu_addr -= pcie->mem_res->start;
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addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
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(lower_32_bits(cpu_addr) & GENMASK(31, 8));
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addr1 = upper_32_bits(cpu_addr);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
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}
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static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
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struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
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struct cdns_pcie *pcie = &rc->pcie;
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unsigned int busn = bus->number;
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u32 addr0, desc0;
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if (busn == rc->bus_range->start) {
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/*
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* Only the root port (devfn == 0) is connected to this bus.
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* All other PCI devices are behind some bridge hence on another
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* bus.
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*/
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if (devfn)
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return NULL;
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return pcie->reg_base + (where & 0xfff);
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}
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/* Update Output registers for AXI region 0. */
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addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
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CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) |
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CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(busn);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0);
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/* Configuration Type 0 or Type 1 access. */
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desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
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CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
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/*
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* The bus number was already set once for all in desc1 by
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* cdns_pcie_host_init_address_translation().
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*/
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if (busn == rc->bus_range->start + 1)
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
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else
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1;
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0);
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return rc->cfg_base + (where & 0xfff);
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}
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static struct pci_ops cdns_pcie_host_ops = {
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.map_bus = cdns_pci_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static const struct of_device_id cdns_pcie_host_of_match[] = {
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{ .compatible = "cdns,cdns-pcie-host" },
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{ },
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};
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static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
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{
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struct cdns_pcie *pcie = &rc->pcie;
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u32 value, ctrl;
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/*
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* Set the root complex BAR configuration register:
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* - disable both BAR0 and BAR1.
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* - enable Prefetchable Memory Base and Limit registers in type 1
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* config space (64 bits).
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* - enable IO Base and Limit registers in type 1 config
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* space (32 bits).
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*/
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
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value = CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) |
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CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) |
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CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE |
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CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS |
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CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE |
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CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS;
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cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);
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/* Set root port configuration space */
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if (rc->vendor_id != 0xffff)
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cdns_pcie_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id);
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if (rc->device_id != 0xffff)
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cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id);
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cdns_pcie_rp_writeb(pcie, PCI_CLASS_REVISION, 0);
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cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
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cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
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return 0;
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}
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static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
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{
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struct cdns_pcie *pcie = &rc->pcie;
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struct resource *cfg_res = rc->cfg_res;
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struct resource *mem_res = pcie->mem_res;
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struct resource *bus_range = rc->bus_range;
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struct device *dev = rc->dev;
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struct device_node *np = dev->of_node;
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struct of_pci_range_parser parser;
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struct of_pci_range range;
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u32 addr0, addr1, desc1;
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u64 cpu_addr;
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int r, err;
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/*
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* Reserve region 0 for PCI configure space accesses:
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* OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by
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* cdns_pci_map_bus(), other region registers are set here once for all.
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*/
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addr1 = 0; /* Should be programmed to zero. */
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desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus_range->start);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
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cpu_addr = cfg_res->start - mem_res->start;
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addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
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(lower_32_bits(cpu_addr) & GENMASK(31, 8));
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addr1 = upper_32_bits(cpu_addr);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1);
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err = of_pci_range_parser_init(&parser, np);
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if (err)
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return err;
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r = 1;
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for_each_of_pci_range(&parser, &range) {
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bool is_io;
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if (r >= rc->max_regions)
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break;
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if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
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is_io = false;
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else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
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is_io = true;
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else
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continue;
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cdns_pcie_set_outbound_region(pcie, r, is_io,
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range.cpu_addr,
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range.pci_addr,
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range.size);
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r++;
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}
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/*
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* Set Root Port no BAR match Inbound Translation registers:
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* needed for MSI and DMA.
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* Root Port BAR0 and BAR1 are disabled, hence no need to set their
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* inbound translation registers.
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*/
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addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(rc->no_bar_nbits);
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addr1 = 0;
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(RP_NO_BAR), addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(RP_NO_BAR), addr1);
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return 0;
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}
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static int cdns_pcie_host_init(struct device *dev,
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struct list_head *resources,
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struct cdns_pcie_rc *rc)
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{
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struct resource *bus_range = NULL;
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int err;
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/* Parse our PCI ranges and request their resources */
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err = pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
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if (err)
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return err;
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rc->bus_range = bus_range;
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rc->pcie.bus = bus_range->start;
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err = cdns_pcie_host_init_root_port(rc);
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if (err)
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goto err_out;
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err = cdns_pcie_host_init_address_translation(rc);
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if (err)
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goto err_out;
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return 0;
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err_out:
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pci_free_resource_list(resources);
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return err;
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}
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static int cdns_pcie_host_probe(struct platform_device *pdev)
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{
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const char *type;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct pci_host_bridge *bridge;
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struct list_head resources;
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struct cdns_pcie_rc *rc;
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struct cdns_pcie *pcie;
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struct resource *res;
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int ret;
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
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if (!bridge)
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return -ENOMEM;
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rc = pci_host_bridge_priv(bridge);
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rc->dev = dev;
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pcie = &rc->pcie;
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rc->max_regions = 32;
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of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);
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rc->no_bar_nbits = 32;
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of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits);
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rc->vendor_id = 0xffff;
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of_property_read_u16(np, "vendor-id", &rc->vendor_id);
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rc->device_id = 0xffff;
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of_property_read_u16(np, "device-id", &rc->device_id);
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type = of_get_property(np, "device_type", NULL);
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if (!type || strcmp(type, "pci")) {
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dev_err(dev, "invalid \"device_type\" %s\n", type);
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return -EINVAL;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
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pcie->reg_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(pcie->reg_base)) {
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dev_err(dev, "missing \"reg\"\n");
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return PTR_ERR(pcie->reg_base);
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
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rc->cfg_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(rc->cfg_base)) {
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dev_err(dev, "missing \"cfg\"\n");
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return PTR_ERR(rc->cfg_base);
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}
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rc->cfg_res = res;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
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if (!res) {
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dev_err(dev, "missing \"mem\"\n");
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return -EINVAL;
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}
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pcie->mem_res = res;
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pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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dev_err(dev, "pm_runtime_get_sync() failed\n");
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goto err_get_sync;
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}
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ret = cdns_pcie_host_init(dev, &resources, rc);
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if (ret)
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goto err_init;
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list_splice_init(&resources, &bridge->windows);
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bridge->dev.parent = dev;
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bridge->busnr = pcie->bus;
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bridge->ops = &cdns_pcie_host_ops;
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bridge->map_irq = of_irq_parse_and_map_pci;
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bridge->swizzle_irq = pci_common_swizzle;
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|
||||
ret = pci_host_probe(bridge);
|
||||
if (ret < 0)
|
||||
goto err_host_probe;
|
||||
|
||||
return 0;
|
||||
|
||||
err_host_probe:
|
||||
pci_free_resource_list(&resources);
|
||||
|
||||
err_init:
|
||||
pm_runtime_put_sync(dev);
|
||||
|
||||
err_get_sync:
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver cdns_pcie_host_driver = {
|
||||
.driver = {
|
||||
.name = "cdns-pcie-host",
|
||||
.of_match_table = cdns_pcie_host_of_match,
|
||||
},
|
||||
.probe = cdns_pcie_host_probe,
|
||||
};
|
||||
builtin_platform_driver(cdns_pcie_host_driver);
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
// Copyright (c) 2017 Cadence
|
||||
// Cadence PCIe controller driver.
|
||||
// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
|
||||
|
||||
#ifndef _PCIE_CADENCE_H
|
||||
#define _PCIE_CADENCE_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
/*
|
||||
* Local Management Registers
|
||||
*/
|
||||
#define CDNS_PCIE_LM_BASE 0x00100000
|
||||
|
||||
/* Vendor ID Register */
|
||||
#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)
|
||||
#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
|
||||
#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0
|
||||
#define CDNS_PCIE_LM_ID_VENDOR(vid) \
|
||||
(((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
|
||||
#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
|
||||
#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16
|
||||
#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
|
||||
(((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
|
||||
|
||||
/* Root Port Requestor ID Register */
|
||||
#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
|
||||
#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
|
||||
#define CDNS_PCIE_LM_RP_RID_SHIFT 0
|
||||
#define CDNS_PCIE_LM_RP_RID_(rid) \
|
||||
(((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
|
||||
|
||||
/* Root Complex BAR Configuration Register */
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
|
||||
(((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
|
||||
(((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
|
||||
(((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
|
||||
(((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31)
|
||||
|
||||
/* BAR control values applicable to both Endpoint Function and Root Complex */
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
|
||||
|
||||
|
||||
/*
|
||||
* Root Port Registers (PCI configuration space for the root port function)
|
||||
*/
|
||||
#define CDNS_PCIE_RP_BASE 0x00200000
|
||||
|
||||
|
||||
/*
|
||||
* Address Translation Registers
|
||||
*/
|
||||
#define CDNS_PCIE_AT_BASE 0x00400000
|
||||
|
||||
/* Region r Outbound AXI to PCIe Address Translation Register 0 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
|
||||
(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
|
||||
(((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
|
||||
(((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
|
||||
|
||||
/* Region r Outbound AXI to PCIe Address Translation Register 1 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
|
||||
|
||||
/* Region r Outbound PCIe Descriptor Register 0 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd
|
||||
/* Bit 23 MUST be set in RC mode. */
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
|
||||
(((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
|
||||
|
||||
/* Region r Outbound PCIe Descriptor Register 1 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
|
||||
((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
|
||||
|
||||
/* Region r AXI Region Base Address Register 0 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
|
||||
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
|
||||
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
|
||||
(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
|
||||
|
||||
/* Region r AXI Region Base Address Register 1 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
|
||||
|
||||
/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
|
||||
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
|
||||
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
|
||||
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
|
||||
(((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
|
||||
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
|
||||
|
||||
enum cdns_pcie_rp_bar {
|
||||
RP_BAR0,
|
||||
RP_BAR1,
|
||||
RP_NO_BAR
|
||||
};
|
||||
|
||||
/**
|
||||
* struct cdns_pcie - private data for Cadence PCIe controller drivers
|
||||
* @reg_base: IO mapped register base
|
||||
* @mem_res: start/end offsets in the physical system memory to map PCI accesses
|
||||
* @bus: In Root Complex mode, the bus number
|
||||
*/
|
||||
struct cdns_pcie {
|
||||
void __iomem *reg_base;
|
||||
struct resource *mem_res;
|
||||
u8 bus;
|
||||
};
|
||||
|
||||
/* Register access */
|
||||
static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value)
|
||||
{
|
||||
writeb(value, pcie->reg_base + reg);
|
||||
}
|
||||
|
||||
static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value)
|
||||
{
|
||||
writew(value, pcie->reg_base + reg);
|
||||
}
|
||||
|
||||
static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
|
||||
{
|
||||
writel(value, pcie->reg_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
|
||||
{
|
||||
return readl(pcie->reg_base + reg);
|
||||
}
|
||||
|
||||
/* Root Port register access */
|
||||
static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
|
||||
u32 reg, u8 value)
|
||||
{
|
||||
writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
|
||||
}
|
||||
|
||||
static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
|
||||
u32 reg, u16 value)
|
||||
{
|
||||
writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
|
||||
}
|
||||
|
||||
#endif /* _PCIE_CADENCE_H */
|
||||
Loading…
Reference in New Issue