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V4L/DVB (13545): em28xx: properly select IR protocol based on the IR table 

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
hifive-unleashed-5.1
Mauro Carvalho Chehab 2009-12-05 08:27:49 -03:00
parent 4039ff28a5
commit 1bad429e81
3 changed files with 16 additions and 5 deletions
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2
drivers/media/video/em28xx/em28xx-core.c
View File

@ -216,7 +216,7 @@ int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
* sets only some bits (specified by bitmask) of a register, by first reading
* the actual value
*/
static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
u8 bitmask)
{
int oldval;

17
drivers/media/video/em28xx/em28xx-input.c
View File

@ -337,19 +337,28 @@ int em28xx_ir_init(struct em28xx *dev)
goto err_out_free;
ir->input = input_dev;
ir_config = EM2874_IR_RC5;
/* Adjust xclk based o IR table for RC5/NEC tables */
if (dev->board.ir_codes->ir_type == IR_TYPE_RC5) {
dev->board.xclk |= EM28XX_XCLK_IR_RC5_MODE;
ir->full_code = 1;
} else if (dev->board.ir_codes->ir_type == IR_TYPE_NEC) {
dev->board.xclk &= ~EM28XX_XCLK_IR_RC5_MODE;
ir_config = EM2874_IR_NEC;
ir->full_code = 1;
}
em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, dev->board.xclk,
EM28XX_XCLK_IR_RC5_MODE);
/* Setup the proper handler based on the chip */
switch (dev->chip_id) {
case CHIP_ID_EM2860:
case CHIP_ID_EM2883:
if (dev->model == EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950)
ir->full_code = 1;
ir->get_key = default_polling_getkey;
break;
case CHIP_ID_EM2874:
ir->get_key = em2874_polling_getkey;
/* For now we only support RC5, so enable it */
ir_config = EM2874_IR_RC5;
em28xx_write_regs(dev, EM2874_R50_IR_CONFIG, &ir_config, 1);
break;
default:

2
drivers/media/video/em28xx/em28xx.h
View File

@ -643,6 +643,8 @@ int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
int len);
int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len);
int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val);
int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
u8 bitmask);
int em28xx_read_ac97(struct em28xx *dev, u8 reg);
int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val);