MLK-23954-1 arm64: dts: add i.MX8MN LPDDR4 EVK root/inmate dts
Add root/inmate dts. They are almost same as i.MX8MN DDR4 jailhouse dts. Acked-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>5.4-rM2-2.2.x-imx-squashed
Peng Fan
parent
1d808717bb
commit
1bae6cf2bf
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@ -57,7 +57,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-ddr4-evk.dtb imx8mn-ddr4-evk-ak5558.dtb \
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imx8mn-ddr4-evk-rm67191.dtb imx8mn-ddr4-evk-rpmsg.dtb imx8mn-ddr4-evk-usd-wifi.dtb \
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imx8mn-evk-ak5558.dtb imx8mn-evk-rpmsg.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk-root.dtb imx8mn-ddr4-evk-inmate.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk-root.dtb imx8mn-ddr4-evk-inmate.dtb imx8mn-evk-root.dtb imx8mn-evk-inmate.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.dtb imx8mp-evk-rpmsg.dtb \
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imx8mp-evk-rm67191.dtb imx8mp-evk-flexcan2.dtb imx8mp-evk-it6263-lvds-dual-channel.dtb \
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imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-ab2.dtb imx8mp-evk-sof-wm8960.dtb \
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@ -0,0 +1,171 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2020 NXP
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Freescale i.MX8MN EVK";
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compatible = "fsl,imx8mn-evk", "fsl,imx8mm";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial3 = &uart4;
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mmc2 = &usdhc3;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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A53_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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clock-latency = <61036>;
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next-level-cache = <&A53_L2>;
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enable-method = "psci";
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#cooling-cells = <2>;
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};
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A53_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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clock-latency = <61036>;
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next-level-cache = <&A53_L2>;
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enable-method = "psci";
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#cooling-cells = <2>;
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};
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A53_L2: l2-cache0 {
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compatible = "cache";
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};
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};
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osc_24m: clock-osc-24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc_24m";
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};
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gic: interrupt-controller@38800000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
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<0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
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clock-frequency = <8333333>;
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};
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clk_dummy: clock@7 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "clk_dummy";
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};
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/* The clocks are configured by 1st OS */
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clk_200m: clock@8 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "200m";
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};
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clk_266m: clock@9 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <266000000>;
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clock-output-names = "266m";
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};
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clk_80m: clock@10 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <80000000>;
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clock-output-names = "80m";
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};
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pci@bb800000 {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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bus-range = <0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
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reg = <0x0 0xbb800000 0x0 0x100000>;
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ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x3e000000>;
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dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
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aips3: bus@30800000 {
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compatible = "fsl,imx8mq-aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x30800000 0x30800000 0x400000>,
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<0x08000000 0x08000000 0x10000000>;
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uart4: serial@30a60000 {
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compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
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reg = <0x30a60000 0x10000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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usdhc3: mmc@30b60000 {
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compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc";
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reg = <0x30b60000 0x10000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "ipg", "ahb", "per";
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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bus-width = <4>;
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status = "disabled";
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};
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};
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};
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};
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&uart4 {
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clocks = <&osc_24m>,
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<&osc_24m>;
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clock-names = "ipg", "per";
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/delete-property/ dmas;
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/delete-property/ dmas-names;
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status = "okay";
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};
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&usdhc3 {
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clocks = <&clk_dummy>,
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<&clk_266m>,
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<&clk_200m>;
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/delete-property/assigned-clocks;
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/delete-property/assigned-clock-rates;
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clock-names = "ipg", "ahb", "per";
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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@ -0,0 +1,90 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2020 NXP
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*/
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#include "imx8mn-evk.dts"
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&{/} {
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x28000000>;
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alloc-ranges = <0 0x40000000 0 0x93c00000>;
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linux,cma-default;
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};
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ivshmem_reserved: ivshmem@0xbbb00000 {
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no-map;
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reg = <0 0xbbb00000 0x0 0x00100000>;
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};
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ivshmem2_reserved: ivshmem2@0xbba00000 {
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no-map;
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reg = <0 0xbba00000 0x0 0x00100000>;
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};
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pci_reserved: pci@0xbb800000 {
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no-map;
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reg = <0 0xbb800000 0x0 0x00200000>;
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};
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loader_reserved: loader@0xbb700000 {
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no-map;
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reg = <0 0xbb700000 0x0 0x00100000>;
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};
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jh_reserved: jh@0xb7c00000 {
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no-map;
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reg = <0 0xb7c00000 0x0 0x00400000>;
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};
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/* 512MB */
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inmate_reserved: inmate@0x93c00000 {
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no-map;
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reg = <0 0x93c00000 0x0 0x24000000>;
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};
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};
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};
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&iomuxc {
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/*
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* Used for the 2nd Linux.
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* TODO: M4 may use these pins.
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*/
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imx8mn-evk {
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
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MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
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>;
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};
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};
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};
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&clk {
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init-on-array = <IMX8MN_CLK_NAND_USDHC_BUS
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IMX8MN_CLK_USDHC3_ROOT
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IMX8MN_CLK_UART4_ROOT>;
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};
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&uart2 {
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pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>;
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assigned-clocks = <&clk IMX8MN_CLK_UART4>;
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assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
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};
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&usdhc3 {
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status = "disabled";
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};
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&usdhc2 {
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pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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};
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