From 1bda33273eccae3c0d878d34660eca9da1765db0 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 27 May 2020 10:11:08 +0800 Subject: [PATCH] MLK-24171-1 arm64: dts: imx8mp: verify the pcie pll sys ref clock Verify the PCIe PLL_SYS reference clock source on EVK board. The external OSC clock is used as PCIe REF clock source in default. NOTE: Change the ext_osc of pcie/pcie_phy to '0' when enable SYS_PLL clock mode. Signed-off-by: Richard Zhu Reviewed-by: Fugang Duan --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 5 +++-- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 98bb4c47e084..998456017731 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -674,7 +674,7 @@ pinctrl-0 = <&pinctrl_pcie>; disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; - ext_osc = <0>; + ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, <&clk IMX8MP_CLK_PCIE_AUX>, <&clk IMX8MP_CLK_PCIE_PHY>, @@ -691,7 +691,7 @@ &pcie_ep{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - ext_osc = <0>; + ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, <&clk IMX8MP_CLK_PCIE_AUX>, <&clk IMX8MP_CLK_PCIE_PHY>, @@ -705,6 +705,7 @@ }; &pcie_phy{ + ext_osc = <1>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9175639d6e45..652ff82b4466 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1936,7 +1936,7 @@ <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <3>; + fsl,max-link-speed = <2>; power-domains = <&pcie_pd>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIEPHY_PERST>,