bnx2x: Flow control enhancement
Setting better HW thresholds and enabling FW capabilities for better enforcement. Also set the HW to more efficiently use the internal buffers if this is a single port design Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Eilon Greenstein
David S. Miller
parent
8a1c38d17d
commit
1c06328c03
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@ -846,7 +846,7 @@ struct bnx2x {
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u32 flags;
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#define PCIX_FLAG 1
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#define PCI_32BIT_FLAG 2
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#define ONE_TDMA_FLAG 4 /* no longer used */
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#define ONE_PORT_FLAG 4
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#define NO_WOL_FLAG 8
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#define USING_DAC_FLAG 0x10
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#define USING_MSIX_FLAG 0x20
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@ -107,6 +107,9 @@
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#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
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((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
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#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
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(IS_E1H_OFFSET ? (0x8020 + (port * 0x4b0) + (clientId * 0x30)) : \
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0xffffffff)
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#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1d98 + \
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(function * 0x8)))
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@ -120,6 +123,8 @@
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#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \
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(function * 0x8)))
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#define USTORM_PAUSE_ENABLED_OFFSET(port) \
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(IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
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#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
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(IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
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0x28)) : (0x4740 + (port * 0x2d0) + (stats_counter_id * 0x28)))
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@ -2614,6 +2614,41 @@ struct tstorm_eth_tpa_exist {
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};
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/*
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* rx rings pause data for E1h only
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*/
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struct ustorm_eth_rx_pause_data_e1h {
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#if defined(__BIG_ENDIAN)
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u16 bd_thr_low;
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u16 cqe_thr_low;
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#elif defined(__LITTLE_ENDIAN)
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u16 cqe_thr_low;
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u16 bd_thr_low;
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#endif
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#if defined(__BIG_ENDIAN)
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u16 cos;
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u16 sge_thr_low;
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#elif defined(__LITTLE_ENDIAN)
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u16 sge_thr_low;
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u16 cos;
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#endif
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#if defined(__BIG_ENDIAN)
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u16 bd_thr_high;
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u16 cqe_thr_high;
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#elif defined(__LITTLE_ENDIAN)
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u16 cqe_thr_high;
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u16 bd_thr_high;
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#endif
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#if defined(__BIG_ENDIAN)
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u16 reserved0;
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u16 sge_thr_high;
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#elif defined(__LITTLE_ENDIAN)
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u16 sge_thr_high;
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u16 reserved0;
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#endif
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};
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/*
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* Three RX producers for ETH
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*/
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@ -2165,6 +2165,19 @@ static void bnx2x_link_attn(struct bnx2x *bp)
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if (bp->link_vars.link_up) {
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/* dropless flow control */
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if (CHIP_IS_E1H(bp)) {
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int port = BP_PORT(bp);
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u32 pause_enabled = 0;
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if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
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pause_enabled = 1;
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REG_WR(bp, BAR_USTRORM_INTMEM +
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USTORM_PAUSE_ENABLED_OFFSET(port),
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pause_enabled);
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}
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if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
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struct host_port_stats *pstats;
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@ -4909,6 +4922,38 @@ static void bnx2x_init_internal_func(struct bnx2x *bp)
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max_agg_size);
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}
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/* dropless flow control */
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if (CHIP_IS_E1H(bp)) {
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struct ustorm_eth_rx_pause_data_e1h rx_pause = {0};
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rx_pause.bd_thr_low = 250;
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rx_pause.cqe_thr_low = 250;
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rx_pause.cos = 1;
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rx_pause.sge_thr_low = 0;
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rx_pause.bd_thr_high = 350;
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rx_pause.cqe_thr_high = 350;
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rx_pause.sge_thr_high = 0;
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for_each_rx_queue(bp, i) {
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struct bnx2x_fastpath *fp = &bp->fp[i];
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if (!fp->disable_tpa) {
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rx_pause.sge_thr_low = 150;
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rx_pause.sge_thr_high = 250;
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}
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offset = BAR_USTRORM_INTMEM +
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USTORM_ETH_RING_PAUSE_DATA_OFFSET(port,
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fp->cl_id);
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for (j = 0;
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j < sizeof(struct ustorm_eth_rx_pause_data_e1h)/4;
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j++)
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REG_WR(bp, offset + j*4,
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((u32 *)&rx_pause)[j]);
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}
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}
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memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
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/* Init rate shaping and fairness contexts */
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@ -5437,14 +5482,6 @@ static int bnx2x_init_common(struct bnx2x *bp)
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}
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bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
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if (CHIP_REV_IS_SLOW(bp)) {
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/* fix for emulation and FPGA for no pause */
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REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
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REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513);
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REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0);
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REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
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}
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bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
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REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
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/* set NIC mode */
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@ -5626,6 +5663,7 @@ static int bnx2x_init_common(struct bnx2x *bp)
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static int bnx2x_init_port(struct bnx2x *bp)
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{
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int port = BP_PORT(bp);
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u32 low, high;
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u32 val;
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DP(BNX2X_MSG_MCP, "starting port init port %x\n", port);
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@ -5672,7 +5710,32 @@ static int bnx2x_init_port(struct bnx2x *bp)
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func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
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#endif
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/* Port DQ comes here */
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/* Port BRB1 comes here */
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bnx2x_init_block(bp, (port ? BRB1_PORT1_START : BRB1_PORT0_START),
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(port ? BRB1_PORT1_END : BRB1_PORT0_END));
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if (CHIP_REV_IS_SLOW(bp) && !CHIP_IS_E1H(bp)) {
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/* no pause for emulation and FPGA */
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low = 0;
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high = 513;
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} else {
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if (IS_E1HMF(bp))
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low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
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else if (bp->dev->mtu > 4096) {
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if (bp->flags & ONE_PORT_FLAG)
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low = 160;
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else {
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val = bp->dev->mtu;
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/* (24*1024 + val*4)/256 */
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low = 96 + (val/64) + ((val % 64) ? 1 : 0);
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}
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} else
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low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
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high = low + 56; /* 14*1024/256 */
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}
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REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
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REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
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/* Port PRS comes here */
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/* Port TSDM comes here */
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/* Port CSDM comes here */
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@ -5754,6 +5817,14 @@ static int bnx2x_init_port(struct bnx2x *bp)
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REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
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(IS_E1HMF(bp) ? 0x1 : 0x2));
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/* support pause requests from USDM, TSDM and BRB */
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REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 + port*4, 0x7);
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{
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REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
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REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
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REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
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}
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}
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/* Port MCP comes here */
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@ -7331,6 +7402,13 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
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bp->link_params.chip_id = bp->common.chip_id;
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BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
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val = (REG_RD(bp, 0x2874) & 0x55);
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if ((bp->common.chip_id & 0x1) ||
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(CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
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bp->flags |= ONE_PORT_FLAG;
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BNX2X_DEV_INFO("single port device\n");
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}
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val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
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bp->common.flash_size = (NVRAM_1MB_SIZE <<
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(val & MCPR_NVM_CFG4_FLASH_SIZE));
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@ -30,8 +30,20 @@
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address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
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BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
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#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
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/* [RW 10] The number of free blocks above which the High_llfc signal to
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interface #n is de-asserted. */
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#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
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/* [RW 10] The number of free blocks below which the High_llfc signal to
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interface #n is asserted. */
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#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
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/* [RW 23] LL RAM data. */
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#define BRB1_REG_LL_RAM 0x61000
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/* [RW 10] The number of free blocks above which the Low_llfc signal to
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interface #n is de-asserted. */
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#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
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/* [RW 10] The number of free blocks below which the Low_llfc signal to
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interface #n is asserted. */
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#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
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/* [R 24] The number of full blocks. */
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#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
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/* [ST 32] The number of cycles that the write_full signal towards MAC #0
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@ -1684,6 +1696,19 @@
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/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
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9-11PHY7; 12 MAC4; 13-15 PHY10; */
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#define NIG_REG_LED_MODE_P0 0x102f0
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/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
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tsdm enable; b2- usdm enable */
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#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
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/* [RW 1] SAFC enable for port0. This register may get 1 only when
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~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
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port */
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#define NIG_REG_LLFC_ENABLE_0 0x16208
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/* [RW 16] classes are high-priority for port0 */
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#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
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/* [RW 16] classes are low-priority for port0 */
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#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
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/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
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#define NIG_REG_LLFC_OUT_EN_0 0x160c8
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#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
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#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
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#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
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@ -1754,6 +1779,10 @@
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#define NIG_REG_NIG_INT_STS_1 0x103c0
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/* [R 32] Parity register #0 read */
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#define NIG_REG_NIG_PRTY_STS 0x103d0
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/* [RW 1] Pause enable for port0. This register may get 1 only when
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~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
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port */
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#define NIG_REG_PAUSE_ENABLE_0 0x160c0
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/* [RW 1] Input enable for RX PBF LP IF */
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#define NIG_REG_PBF_LB_IN_EN 0x100b4
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/* [RW 1] Value of this register will be transmitted to port swap when
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