Blackfin arch: add missing implementations SIC_IWR crosses several registers
SIC_IWR crosses several registers - add missing implementations - make sure SIC_IWR is SET after boot Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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@ -371,6 +371,9 @@ int __init init_arch_irq(void)
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bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
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SSYNC();
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bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
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bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
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local_irq_disable();
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init_exception_buff();
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@ -472,8 +472,12 @@ int __init init_arch_irq(void)
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bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
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bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
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bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
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bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
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bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
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bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
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#else
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bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
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bfin_write_SIC_IWR(IWR_ENABLE_ALL);
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#endif
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SSYNC();
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@ -32,6 +32,7 @@
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#define _CDEF_BF54X_H
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#include "defBF54x_base.h"
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#include <asm/system.h>
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/* ************************************************************** */
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/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
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@ -44,7 +45,31 @@
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#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
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#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
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#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
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#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1, iwr2;
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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iwr2 = bfin_read32(SIC_IWR2);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write32(SIC_IWR2, 0);
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bfin_write16(VR_CTL, val);
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__builtin_bfin_ssync();
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local_irq_save(flags);
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asm("IDLE;");
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local_irq_restore(flags);
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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bfin_write32(SIC_IWR2, iwr2);
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}
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#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
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#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
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#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
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@ -57,12 +57,14 @@
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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unsigned long flags, iwr0, iwr1;
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SICA_IWR0);
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iwr0 = bfin_read32(SICA_IWR0);
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iwr1 = bfin_read32(SICA_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SICA_IWR0, IWR_ENABLE(0));
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bfin_write32(SICA_IWR1, 0);
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bfin_write16(VR_CTL, val);
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__builtin_bfin_ssync();
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@ -70,7 +72,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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local_irq_save(flags);
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asm("IDLE;");
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local_irq_restore(flags);
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bfin_write32(SICA_IWR0, iwr);
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bfin_write32(SICA_IWR0, iwr0);
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bfin_write32(SICA_IWR1, iwr1);
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}
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#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
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#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
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