drm/i915: initialization/teardown for the aliasing ppgtt
This just adds the setup and teardown code for the ppgtt PDE and the last-level pagetables, which are fixed for the entire lifetime, at least for the moment. v2: Kill the stray debug printk noted by and improve the pte definitions as suggested by Chris Wilson. v3: Clean up the aperture stealing code as noted by Ben Widawsky. v4: Paint the init code in a more pleasing colour as suggest by Chris Wilson. v5: Explain the magic numbers noticed by Ben Widawsky. Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
428ccb21b7
commit
1d2a314c97
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@ -1196,22 +1196,39 @@ static int i915_load_gem_init(struct drm_device *dev)
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/* Basic memrange allocator for stolen space */
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drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
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/* Let GEM Manage all of the aperture.
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*
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* However, leave one page at the end still bound to the scratch page.
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* There are a number of places where the hardware apparently
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* prefetches past the end of the object, and we've seen multiple
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* hangs with the GPU head pointer stuck in a batchbuffer bound
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* at the last page of the aperture. One page should be enough to
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* keep any prefetching inside of the aperture.
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*/
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i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
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if (HAS_ALIASING_PPGTT(dev)) {
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/* PPGTT pdes are stolen from global gtt ptes, so shrink the
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* aperture accordingly when using aliasing ppgtt. */
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gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
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/* For paranoia keep the guard page in between. */
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gtt_size -= PAGE_SIZE;
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i915_gem_do_init(dev, 0, mappable_size, gtt_size);
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ret = i915_gem_init_aliasing_ppgtt(dev);
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if (ret)
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return ret;
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} else {
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/* Let GEM Manage all of the aperture.
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*
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* However, leave one page at the end still bound to the scratch
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* page. There are a number of places where the hardware
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* apparently prefetches past the end of the object, and we've
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* seen multiple hangs with the GPU head pointer stuck in a
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* batchbuffer bound at the last page of the aperture. One page
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* should be enough to keep any prefetching inside of the
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* aperture.
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*/
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i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
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}
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mutex_lock(&dev->struct_mutex);
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ret = i915_gem_init_hw(dev);
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mutex_unlock(&dev->struct_mutex);
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if (ret)
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if (ret) {
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i915_gem_cleanup_aliasing_ppgtt(dev);
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return ret;
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}
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/* Try to set up FBC with a reasonable compressed buffer size */
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if (I915_HAS_FBC(dev) && i915_powersave) {
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@ -1298,6 +1315,7 @@ cleanup_gem:
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mutex_lock(&dev->struct_mutex);
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i915_gem_cleanup_ringbuffer(dev);
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mutex_unlock(&dev->struct_mutex);
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i915_gem_cleanup_aliasing_ppgtt(dev);
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cleanup_vga_switcheroo:
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vga_switcheroo_unregister_client(dev->pdev);
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cleanup_vga_client:
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@ -2184,6 +2202,7 @@ int i915_driver_unload(struct drm_device *dev)
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i915_gem_free_all_phys_object(dev);
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i915_gem_cleanup_ringbuffer(dev);
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mutex_unlock(&dev->struct_mutex);
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i915_gem_cleanup_aliasing_ppgtt(dev);
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if (I915_HAS_FBC(dev) && i915_powersave)
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i915_cleanup_compression(dev);
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drm_mm_takedown(&dev_priv->mm.stolen);
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@ -258,6 +258,16 @@ struct intel_device_info {
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u8 has_llc:1;
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};
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#define I915_PPGTT_PD_ENTRIES 512
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#define I915_PPGTT_PT_ENTRIES 1024
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struct i915_hw_ppgtt {
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unsigned num_pd_entries;
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struct page **pt_pages;
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uint32_t pd_offset;
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dma_addr_t *pt_dma_addr;
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dma_addr_t scratch_page_dma_addr;
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};
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enum no_fbc_reason {
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FBC_NO_OUTPUT, /* no outputs enabled to compress */
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FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
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@ -578,6 +588,9 @@ typedef struct drm_i915_private {
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struct io_mapping *gtt_mapping;
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int gtt_mtrr;
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/** PPGTT used for aliasing the PPGTT with the GTT */
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struct i915_hw_ppgtt *aliasing_ppgtt;
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struct shrinker inactive_shrinker;
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/**
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@ -973,6 +986,8 @@ struct drm_i915_file_private {
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#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
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#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
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#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
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#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
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#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
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@ -1232,6 +1247,9 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
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enum i915_cache_level cache_level);
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/* i915_gem_gtt.c */
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int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
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void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
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void i915_gem_restore_gtt_mappings(struct drm_device *dev);
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int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
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void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
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@ -29,6 +29,145 @@
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#include "i915_trace.h"
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#include "intel_drv.h"
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/* PPGTT support for Sandybdrige/Gen6 and later */
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static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
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unsigned first_entry,
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unsigned num_entries)
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{
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int i, j;
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uint32_t *pt_vaddr;
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uint32_t scratch_pte;
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scratch_pte = GEN6_PTE_ADDR_ENCODE(ppgtt->scratch_page_dma_addr);
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scratch_pte |= GEN6_PTE_VALID | GEN6_PTE_CACHE_LLC;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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pt_vaddr = kmap_atomic(ppgtt->pt_pages[i]);
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for (j = 0; j < I915_PPGTT_PT_ENTRIES; j++)
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pt_vaddr[j] = scratch_pte;
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kunmap_atomic(pt_vaddr);
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}
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}
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int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_hw_ppgtt *ppgtt;
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uint32_t pd_entry;
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unsigned first_pd_entry_in_global_pt;
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uint32_t __iomem *pd_addr;
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int i;
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int ret = -ENOMEM;
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/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
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* entries. For aliasing ppgtt support we just steal them at the end for
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* now. */
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first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES;
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ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
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if (!ppgtt)
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return ret;
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ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
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ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
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GFP_KERNEL);
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if (!ppgtt->pt_pages)
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goto err_ppgtt;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
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if (!ppgtt->pt_pages[i])
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goto err_pt_alloc;
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}
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if (dev_priv->mm.gtt->needs_dmar) {
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ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t)
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*ppgtt->num_pd_entries,
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GFP_KERNEL);
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if (!ppgtt->pt_dma_addr)
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goto err_pt_alloc;
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}
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pd_addr = dev_priv->mm.gtt->gtt + first_pd_entry_in_global_pt;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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dma_addr_t pt_addr;
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if (dev_priv->mm.gtt->needs_dmar) {
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pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i],
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0, 4096,
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PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev,
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pt_addr)) {
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ret = -EIO;
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goto err_pd_pin;
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}
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ppgtt->pt_dma_addr[i] = pt_addr;
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} else
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pt_addr = page_to_phys(ppgtt->pt_pages[i]);
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pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
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pd_entry |= GEN6_PDE_VALID;
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writel(pd_entry, pd_addr + i);
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}
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readl(pd_addr);
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ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;
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i915_ppgtt_clear_range(ppgtt, 0,
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ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
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ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(uint32_t);
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dev_priv->mm.aliasing_ppgtt = ppgtt;
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return 0;
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err_pd_pin:
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if (ppgtt->pt_dma_addr) {
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for (i--; i >= 0; i--)
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pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
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4096, PCI_DMA_BIDIRECTIONAL);
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}
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err_pt_alloc:
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kfree(ppgtt->pt_dma_addr);
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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if (ppgtt->pt_pages[i])
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__free_page(ppgtt->pt_pages[i]);
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}
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kfree(ppgtt->pt_pages);
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err_ppgtt:
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kfree(ppgtt);
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return ret;
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}
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void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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int i;
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if (!ppgtt)
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return;
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if (ppgtt->pt_dma_addr) {
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for (i = 0; i < ppgtt->num_pd_entries; i++)
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pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
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4096, PCI_DMA_BIDIRECTIONAL);
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}
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kfree(ppgtt->pt_dma_addr);
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for (i = 0; i < ppgtt->num_pd_entries; i++)
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__free_page(ppgtt->pt_pages[i]);
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kfree(ppgtt->pt_pages);
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kfree(ppgtt);
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}
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/* XXX kill agp_type! */
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static unsigned int cache_level_to_agp_type(struct drm_device *dev,
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enum i915_cache_level cache_level)
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@ -92,6 +92,22 @@
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#define GEN6_GRDOM_MEDIA (1 << 2)
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#define GEN6_GRDOM_BLT (1 << 3)
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/* PPGTT stuff */
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#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
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#define GEN6_PDE_VALID (1 << 0)
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#define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */
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/* gen6+ has bit 11-4 for physical addr bit 39-32 */
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#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define GEN6_PTE_VALID (1 << 0)
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#define GEN6_PTE_UNCACHED (1 << 1)
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#define GEN6_PTE_CACHE_LLC (2 << 1)
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#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
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#define GEN6_PTE_CACHE_BITS (3 << 1)
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#define GEN6_PTE_GFDT (1 << 3)
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#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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/* VGA stuff */
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#define VGA_ST01_MDA 0x3ba
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