USB: early: Handle AMD's spec-compliant identifiers, too
commit5.4-rM2-2.2.x-imx-squashed7dbdb53d72
upstream. This fixes a bug that causes the USB3 early console to freeze after printing a single line on AMD machines because it can't parse the Transfer TRB properly. The spec at https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf says in section "4.5.1 Device Context Index" that the Context Index, also known as Endpoint ID according to section "1.6 Terms and Abbreviations", is normally computed as `DCI = (Endpoint Number * 2) + Direction`, which matches the current definitions of XDBC_EPID_OUT and XDBC_EPID_IN. However, the numbering in a Debug Capability Context data structure is supposed to be different: Section "7.6.3.2 Endpoint Contexts and Transfer Rings" explains that a Debug Capability Context data structure has the endpoints mapped to indices 0 and 1. Change XDBC_EPID_OUT/XDBC_EPID_IN to the spec-compliant values, add XDBC_EPID_OUT_INTEL/XDBC_EPID_IN_INTEL with Intel's incorrect values, and let xdbc_handle_tx_event() handle both. I have verified that with this patch applied, the USB3 early console works on both an Intel and an AMD machine. Fixes:aeb9dd1de9
("usb/early: Add driver for xhci debug capability") Cc: stable@vger.kernel.org Signed-off-by: Jann Horn <jannh@google.com> Link: https://lore.kernel.org/r/20200401074619.8024-1-jannh@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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8409f83e3e
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1d53402d89
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@ -728,19 +728,19 @@ static void xdbc_handle_tx_event(struct xdbc_trb *evt_trb)
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case COMP_USB_TRANSACTION_ERROR:
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case COMP_STALL_ERROR:
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default:
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if (ep_id == XDBC_EPID_OUT)
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if (ep_id == XDBC_EPID_OUT || ep_id == XDBC_EPID_OUT_INTEL)
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xdbc.flags |= XDBC_FLAGS_OUT_STALL;
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if (ep_id == XDBC_EPID_IN)
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if (ep_id == XDBC_EPID_IN || ep_id == XDBC_EPID_IN_INTEL)
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xdbc.flags |= XDBC_FLAGS_IN_STALL;
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xdbc_trace("endpoint %d stalled\n", ep_id);
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break;
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}
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if (ep_id == XDBC_EPID_IN) {
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if (ep_id == XDBC_EPID_IN || ep_id == XDBC_EPID_IN_INTEL) {
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xdbc.flags &= ~XDBC_FLAGS_IN_PROCESS;
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xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true);
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} else if (ep_id == XDBC_EPID_OUT) {
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} else if (ep_id == XDBC_EPID_OUT || ep_id == XDBC_EPID_OUT_INTEL) {
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xdbc.flags &= ~XDBC_FLAGS_OUT_PROCESS;
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} else {
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xdbc_trace("invalid endpoint id %d\n", ep_id);
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@ -120,8 +120,22 @@ struct xdbc_ring {
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u32 cycle_state;
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};
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#define XDBC_EPID_OUT 2
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#define XDBC_EPID_IN 3
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/*
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* These are the "Endpoint ID" (also known as "Context Index") values for the
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* OUT Transfer Ring and the IN Transfer Ring of a Debug Capability Context data
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* structure.
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* According to the "eXtensible Host Controller Interface for Universal Serial
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* Bus (xHCI)" specification, section "7.6.3.2 Endpoint Contexts and Transfer
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* Rings", these should be 0 and 1, and those are the values AMD machines give
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* you; but Intel machines seem to use the formula from section "4.5.1 Device
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* Context Index", which is supposed to be used for the Device Context only.
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* Luckily the values from Intel don't overlap with those from AMD, so we can
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* just test for both.
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*/
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#define XDBC_EPID_OUT 0
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#define XDBC_EPID_IN 1
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#define XDBC_EPID_OUT_INTEL 2
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#define XDBC_EPID_IN_INTEL 3
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struct xdbc_state {
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u16 vendor;
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