e1000e: rework disable K1 at 1000Mbps for 82577/82578
This patch reworks a previous workaround (commit 7d3cabbcc) for an issue
in hardware where noise on the interconnect between the MAC and PHY could
be generated by a lower power mode (K1) at 1000Mbps resulting in bad
packets. Disable K1 while at 1000 Mbps but keep it enabled for 10/100Mbps
and when the cable is disconnected. The original version of this
workaround was found to be incomplete.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
hifive-unleashed-5.1
Bruce Allan
David S. Miller
parent
f523d2114e
commit
1d5846b921
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@ -76,6 +76,7 @@
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/* Extended Device Control */
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#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
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#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
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#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
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#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
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#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
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#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
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@ -141,6 +141,20 @@ struct e1000_info;
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#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
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#define HV_TNCRS_LOWER PHY_REG(778, 30)
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/* BM PHY Copper Specific Status */
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#define BM_CS_STATUS 17
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#define BM_CS_STATUS_LINK_UP 0x0400
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#define BM_CS_STATUS_RESOLVED 0x0800
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#define BM_CS_STATUS_SPEED_MASK 0xC000
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#define BM_CS_STATUS_SPEED_1000 0x8000
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/* 82577 Mobile Phy Status Register */
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#define HV_M_STATUS 26
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#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
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#define HV_M_STATUS_SPEED_MASK 0x0300
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#define HV_M_STATUS_SPEED_1000 0x0200
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#define HV_M_STATUS_LINK_UP 0x0040
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enum e1000_boards {
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board_82571,
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board_82572,
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@ -903,6 +903,7 @@ struct e1000_shadow_ram {
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struct e1000_dev_spec_ich8lan {
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bool kmrn_lock_loss_workaround_enabled;
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struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
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bool nvm_k1_enabled;
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};
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struct e1000_hw {
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@ -140,6 +140,9 @@
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#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
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#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
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#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
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#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
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/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
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/* Offset 04h HSFSTS */
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union ich8_hws_flash_status {
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@ -220,6 +223,8 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
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static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
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static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
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static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
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static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
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static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
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static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
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{
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@ -495,14 +500,6 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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goto out;
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}
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if (hw->mac.type == e1000_pchlan) {
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ret_val = e1000e_write_kmrn_reg(hw,
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E1000_KMRNCTRLSTA_K1_CONFIG,
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E1000_KMRNCTRLSTA_K1_ENABLE);
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if (ret_val)
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goto out;
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}
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/*
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* First we want to see if the MII Status Register reports
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* link. If so, then we want to get the current speed/duplex
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@ -512,6 +509,12 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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if (ret_val)
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goto out;
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if (hw->mac.type == e1000_pchlan) {
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ret_val = e1000_k1_gig_workaround_hv(hw, link);
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if (ret_val)
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goto out;
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}
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if (!link)
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goto out; /* No link detected */
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@ -928,6 +931,141 @@ out:
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return ret_val;
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}
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/**
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* e1000_k1_gig_workaround_hv - K1 Si workaround
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* @hw: pointer to the HW structure
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* @link: link up bool flag
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*
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* If K1 is enabled for 1Gbps, the MAC might stall when transitioning
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* from a lower speed. This workaround disables K1 whenever link is at 1Gig
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* If link is down, the function will restore the default K1 setting located
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* in the NVM.
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**/
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static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
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{
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s32 ret_val = 0;
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u16 status_reg = 0;
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bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
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if (hw->mac.type != e1000_pchlan)
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goto out;
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/* Wrap the whole flow with the sw flag */
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ret_val = hw->phy.ops.acquire_phy(hw);
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if (ret_val)
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goto out;
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/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
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if (link) {
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if (hw->phy.type == e1000_phy_82578) {
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ret_val = hw->phy.ops.read_phy_reg_locked(hw,
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BM_CS_STATUS,
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&status_reg);
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if (ret_val)
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goto release;
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status_reg &= BM_CS_STATUS_LINK_UP |
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BM_CS_STATUS_RESOLVED |
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BM_CS_STATUS_SPEED_MASK;
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if (status_reg == (BM_CS_STATUS_LINK_UP |
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BM_CS_STATUS_RESOLVED |
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BM_CS_STATUS_SPEED_1000))
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k1_enable = false;
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}
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if (hw->phy.type == e1000_phy_82577) {
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ret_val = hw->phy.ops.read_phy_reg_locked(hw,
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HV_M_STATUS,
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&status_reg);
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if (ret_val)
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goto release;
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status_reg &= HV_M_STATUS_LINK_UP |
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HV_M_STATUS_AUTONEG_COMPLETE |
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HV_M_STATUS_SPEED_MASK;
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if (status_reg == (HV_M_STATUS_LINK_UP |
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HV_M_STATUS_AUTONEG_COMPLETE |
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HV_M_STATUS_SPEED_1000))
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k1_enable = false;
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}
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/* Link stall fix for link up */
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ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
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0x0100);
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if (ret_val)
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goto release;
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} else {
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/* Link stall fix for link down */
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ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
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0x4100);
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if (ret_val)
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goto release;
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}
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ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
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release:
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hw->phy.ops.release_phy(hw);
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out:
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return ret_val;
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}
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/**
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* e1000_configure_k1_ich8lan - Configure K1 power state
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* @hw: pointer to the HW structure
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* @enable: K1 state to configure
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*
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* Configure the K1 power state based on the provided parameter.
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* Assumes semaphore already acquired.
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*
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* Success returns 0, Failure returns -E1000_ERR_PHY (-2)
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**/
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static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
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{
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s32 ret_val = 0;
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u32 ctrl_reg = 0;
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u32 ctrl_ext = 0;
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u32 reg = 0;
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u16 kmrn_reg = 0;
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ret_val = e1000e_read_kmrn_reg_locked(hw,
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E1000_KMRNCTRLSTA_K1_CONFIG,
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&kmrn_reg);
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if (ret_val)
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goto out;
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if (k1_enable)
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kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
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else
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kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
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ret_val = e1000e_write_kmrn_reg_locked(hw,
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E1000_KMRNCTRLSTA_K1_CONFIG,
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kmrn_reg);
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if (ret_val)
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goto out;
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udelay(20);
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ctrl_ext = er32(CTRL_EXT);
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ctrl_reg = er32(CTRL);
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reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
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reg |= E1000_CTRL_FRCSPD;
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ew32(CTRL, reg);
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ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
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udelay(20);
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ew32(CTRL, ctrl_reg);
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ew32(CTRL_EXT, ctrl_ext);
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udelay(20);
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out:
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return ret_val;
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}
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/**
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* e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
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* @hw: pointer to the HW structure
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@ -1030,10 +1168,20 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
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ret_val = hw->phy.ops.acquire_phy(hw);
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if (ret_val)
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return ret_val;
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hw->phy.addr = 1;
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e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
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ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
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if (ret_val)
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goto out;
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hw->phy.ops.release_phy(hw);
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/*
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* Configure the K1 Si workaround during phy reset assuming there is
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* link so that it disables K1 if link is in 1Gbps.
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*/
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ret_val = e1000_k1_gig_workaround_hv(hw, true);
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out:
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return ret_val;
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}
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@ -2435,6 +2583,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
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**/
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static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
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{
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struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
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u16 reg;
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u32 ctrl, icr, kab;
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s32 ret_val;
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@ -2470,6 +2619,18 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
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ew32(PBS, E1000_PBS_16K);
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}
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if (hw->mac.type == e1000_pchlan) {
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/* Save the NVM K1 bit setting*/
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ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
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if (ret_val)
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return ret_val;
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if (reg & E1000_NVM_K1_ENABLE)
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dev_spec->nvm_k1_enabled = true;
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else
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dev_spec->nvm_k1_enabled = false;
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}
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ctrl = er32(CTRL);
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if (!e1000_check_reset_block(hw)) {
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@ -2847,14 +3008,6 @@ static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
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if (ret_val)
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return ret_val;
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if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) {
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ret_val = e1000e_write_kmrn_reg(hw,
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E1000_KMRNCTRLSTA_K1_CONFIG,
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E1000_KMRNCTRLSTA_K1_DISABLE);
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if (ret_val)
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return ret_val;
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}
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if ((hw->mac.type == e1000_ich8lan) &&
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(hw->phy.type == e1000_phy_igp_3) &&
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(*speed == SPEED_1000)) {
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@ -95,13 +95,6 @@ static const u16 e1000_igp_2_cable_length_table[] =
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/* BM PHY Copper Specific Control 1 */
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#define BM_CS_CTRL1 16
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/* BM PHY Copper Specific Status */
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#define BM_CS_STATUS 17
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#define BM_CS_STATUS_LINK_UP 0x0400
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#define BM_CS_STATUS_RESOLVED 0x0800
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#define BM_CS_STATUS_SPEED_MASK 0xC000
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#define BM_CS_STATUS_SPEED_1000 0x8000
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#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
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#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
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#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
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@ -563,7 +556,7 @@ s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
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}
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/**
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* e1000_read_kmrn_reg_locked - Read kumeran register
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* e1000e_read_kmrn_reg_locked - Read kumeran register
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* @hw: pointer to the HW structure
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* @offset: register offset to be read
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* @data: pointer to the read data
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@ -572,7 +565,7 @@ s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
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* information retrieved is stored in data.
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* Assumes semaphore already acquired.
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**/
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s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
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s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
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{
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return __e1000_read_kmrn_reg(hw, offset, data, true);
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}
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@ -631,7 +624,7 @@ s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
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}
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/**
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* e1000_write_kmrn_reg_locked - Write kumeran register
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* e1000e_write_kmrn_reg_locked - Write kumeran register
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* @hw: pointer to the HW structure
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* @offset: register offset to write to
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* @data: data to write at register offset
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@ -639,7 +632,7 @@ s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
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* Write the data to PHY register at the offset using the kumeran interface.
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* Assumes semaphore already acquired.
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**/
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s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
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s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
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{
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return __e1000_write_kmrn_reg(hw, offset, data, true);
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}
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Loading…
Reference in New Issue