pch_can: Improve rx processing
Replace complex "goto" to "do~while". For easy to read/understand, it divides a rx function into some functions. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Tomoya
David S. Miller
parent
8ac9702b9d
commit
1d5b4b2778
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@ -698,83 +698,110 @@ static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
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static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
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{
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if (obj_id < PCH_FIFO_THRESH) {
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iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
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PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
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/* Clearing the Dir bit. */
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pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
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/* Clearing NewDat & IntPnd */
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pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
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PCH_IF_MCONT_INTPND);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id);
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} else if (obj_id > PCH_FIFO_THRESH) {
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pch_can_int_clr(priv, obj_id);
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} else if (obj_id == PCH_FIFO_THRESH) {
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int cnt;
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for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
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pch_can_int_clr(priv, cnt + 1);
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}
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}
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static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
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{
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struct pch_can_priv *priv = netdev_priv(ndev);
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struct net_device_stats *stats = &(priv->ndev->stats);
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struct sk_buff *skb;
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struct can_frame *cf;
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netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
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pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
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PCH_IF_MCONT_MSGLOST);
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iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
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&priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id);
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skb = alloc_can_err_skb(ndev, &cf);
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if (!skb)
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return;
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cf->can_id |= CAN_ERR_CRTL;
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cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
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stats->rx_over_errors++;
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stats->rx_errors++;
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netif_receive_skb(skb);
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}
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static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
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{
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u32 reg;
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canid_t id;
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u32 ide;
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u32 rtr;
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int i, k;
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int rcv_pkts = 0;
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struct sk_buff *skb;
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struct can_frame *cf;
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struct pch_can_priv *priv = netdev_priv(ndev);
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struct net_device_stats *stats = &(priv->ndev->stats);
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int i;
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u32 id2;
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u16 data_reg;
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/* Reading the messsage object from the Message RAM */
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, int_stat);
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do {
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/* Reading the messsage object from the Message RAM */
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_num);
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/* Reading the MCONT register. */
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reg = ioread32(&priv->regs->ifregs[0].mcont);
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reg &= 0xffff;
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/* Reading the MCONT register. */
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reg = ioread32(&priv->regs->ifregs[0].mcont);
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if (reg & PCH_IF_MCONT_EOB)
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break;
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for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) {
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/* If MsgLost bit set. */
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if (reg & PCH_IF_MCONT_MSGLOST) {
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dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
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pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
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PCH_IF_MCONT_MSGLOST);
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iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
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&priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k);
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skb = alloc_can_err_skb(ndev, &cf);
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if (!skb)
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return -ENOMEM;
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priv->can.can_stats.error_passive++;
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priv->can.state = CAN_STATE_ERROR_PASSIVE;
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cf->can_id |= CAN_ERR_CRTL;
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cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
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cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
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stats->rx_packets++;
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stats->rx_bytes += cf->can_dlc;
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netif_receive_skb(skb);
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pch_can_rx_msg_lost(ndev, obj_num);
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rcv_pkts++;
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goto RX_NEXT;
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quota--;
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obj_num++;
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continue;
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} else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
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obj_num++;
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continue;
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}
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if (!(reg & PCH_IF_MCONT_NEWDAT))
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goto RX_NEXT;
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skb = alloc_can_skb(priv->ndev, &cf);
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if (!skb)
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return -ENOMEM;
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/* Get Received data */
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ide = ((ioread32(&priv->regs->ifregs[0].id2)) & PCH_ID2_XTD) >>
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14;
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if (ide) {
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id2 = ioread32(&priv->regs->ifregs[0].id2);
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if (id2 & PCH_ID2_XTD) {
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id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
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id |= (((ioread32(&priv->regs->ifregs[0].id2)) &
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0x1fff) << 16);
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cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
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id |= (((id2) & 0x1fff) << 16);
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cf->can_id = id | CAN_EFF_FLAG;
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} else {
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id = (((ioread32(&priv->regs->ifregs[0].id2)) &
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(CAN_SFF_MASK << 2)) >> 2);
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cf->can_id = (id & CAN_SFF_MASK);
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id = (id2 >> 2) & CAN_SFF_MASK;
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cf->can_id = id;
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}
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rtr = (ioread32(&priv->regs->ifregs[0].id2) & PCH_ID2_DIR);
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if (rtr) {
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cf->can_dlc = 0;
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if (id2 & PCH_ID2_DIR)
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cf->can_id |= CAN_RTR_FLAG;
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} else {
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cf->can_dlc =
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((ioread32(&priv->regs->ifregs[0].mcont)) & 0x0f);
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}
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cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
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ifregs[0].mcont)) & 0xF);
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for (i = 0; i < cf->can_dlc; i += 2) {
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data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
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@ -785,33 +812,12 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
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netif_receive_skb(skb);
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rcv_pkts++;
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stats->rx_packets++;
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quota--;
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stats->rx_bytes += cf->can_dlc;
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if (k < PCH_FIFO_THRESH) {
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iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
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PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
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/* Clearing the Dir bit. */
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pch_can_bit_clear(&priv->regs->ifregs[0].id2,
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PCH_ID2_DIR);
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/* Clearing NewDat & IntPnd */
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pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
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PCH_IF_MCONT_INTPND);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k);
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} else if (k > PCH_FIFO_THRESH) {
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pch_can_int_clr(priv, k);
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} else if (k == PCH_FIFO_THRESH) {
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int cnt;
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for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
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pch_can_int_clr(priv, cnt+1);
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}
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RX_NEXT:
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/* Reading the messsage object from the Message RAM */
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k);
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reg = ioread32(&priv->regs->ifregs[0].mcont);
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}
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pch_fifo_thresh(priv, obj_num);
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obj_num++;
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} while (quota > 0);
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return rcv_pkts;
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}
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@ -869,7 +875,7 @@ static int pch_can_rx_poll(struct napi_struct *napi, int quota)
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goto end;
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if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
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rcv_pkts += pch_can_rx_normal(ndev, int_stat);
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rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
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quota -= rcv_pkts;
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if (quota < 0)
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goto end;
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