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mt2712: 

Add device nodes for usb3, iommu, smi, i2c, spi, pwm,
 mmc, NAND flash and PCIe
 
 mt6797:
 add pinctrl node
 enable uart pins on x20 board
 enable uart pins on EVB
 
 mt7622:
 Add all CPUs to the cooling maps
 
 mt7623a:
 Remove unused binding description
 
 mt7629:
 Add binding description for the SoC and the BananaPi
 based on this chip
 
 mt8173:
 Add all CPUs to the cooling maps
 
 mt8183:
 Add binding description for the SoC
 -----BEGIN PGP SIGNATURE-----
 
 iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAlxd2gYXHG1hdHRoaWFz
 LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00MXBg//VKQgMqIWshMhu7hrD0wkPXZw
 B0BJVlWhywTEisv3oduSL5HOVzKU6pQrWnF+X9PYokwNxz3VkNh3RixaLGsY3JOr
 mkGtx3zAi1qsKYoKH6PNBhJVNCdX8D9SFlBSNOGkK0P5s0kjuPqzk28QU3ehwzdo
 pFjbNadNDL9ySoybFtWGR8UwNkqq0w9acuiZbuRrqzdqkZLdxQ6zDry9P9s+97lA
 WxFQEm+yhGHkpOb1XG75Zw3JBG55L3KymZV+h60wqHvdVCszINZZ9C2c/PqsWGVd
 JzWMJPx2cghfLZdGlr5HQhKD5xM2Swmy2b5co4yRwsSmXdiK2RDkHkkli5CMpiIG
 bt/6v3YffIVV07p/pzWrcOhJex4tCs0w3w24T03FxfCWVNXwb2kIV0Sv8dSBhUku
 aESCBSrU0XAaKmhOPv49ys1oACpvPA9v/QyR+YyQPnK/4c4YezPidhCStvzhoxFG
 a64OID6B1cmhI8PBCecRG22fEmDxktTj/FJ/0nsdbUgwbMXubr2vr9RzJW3B/M+G
 z2ykW6q2K736EWWfKTpzXxfghVSaE90F1leQ3hjIv7h4AuribDw4IJ6ye+uI4Hb/
 jiVHy6TSk8C07jMsvjifs1dL7UF6GIisD+90psuaiYngjilQkaHeDkosybe4qA6n
 +r/pe4bCWvajl37DMXs=
 =xm9P
 -----END PGP SIGNATURE-----

Merge tag 'v5.0-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt2712:
Add device nodes for usb3, iommu, smi, i2c, spi, pwm,
mmc, NAND flash and PCIe

mt6797:
add pinctrl node
enable uart pins on x20 board
enable uart pins on EVB

mt7622:
Add all CPUs to the cooling maps

mt7623a:
Remove unused binding description

mt7629:
Add binding description for the SoC and the BananaPi
based on this chip

mt8173:
Add all CPUs to the cooling maps

mt8183:
Add binding description for the SoC

* tag 'v5.0-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB
  dt-bindings: arm: mediatek: remove unused "mediatek, mt7623a"
  dt-bindings: arm: Add bindings for Mediatek MT8183 SoC Platform
  arm64: dts: add pcie nodes for MT2712
  arm64: dts: add nand nodes for MT2712
  arm64: dts: add mmc nodes for MT2712
  arm64: dts: add pwm nodes for MT2712
  arm64: dts: add spi nodes for MT2712
  arm64: dts: add i2c nodes for MT2712
  arm64: dts: add iommu/smi nodes for MT2712
  arm64: dts: Add USB3 related nodes for MT2712
  ARM64: dts: mediatek: Add all CPUs in cooling maps
  arm64: dts: Add uart for mt6797 EVB
  arm64: dts: mediatek: x20: Add pinmux support for UART1
  arm64: dts: mediatek: mt6797: Add pinctrl support

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
hifive-unleashed-5.1
Arnd Bergmann 2019-02-15 15:54:41 +01:00
parent f7d488be48 858a6c310f
commit 1de741634b
8 changed files with 707 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
Documentation/devicetree/bindings/arm/mediatek.txt
View File

@ -15,11 +15,12 @@ compatible: Must contain one of
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
"mediatek,mt7623" which is referred to MT7623N SoC
"mediatek,mt7623a"
"mediatek,mt7623"
"mediatek,mt7629"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
"mediatek,mt8183"
Supported boards:
@ -57,6 +58,9 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
- Bananapi BPI-R64 for MT7622:
Required root node properties:
- compatible = "bananapi,bpi-r64", "mediatek,mt7622";
- Reference board for MT7623a with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
@ -68,6 +72,9 @@ Supported boards:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
- Bananapi BPI-R2 board:
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
- Reference board for MT7629:
Required root node properties:
- compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
@ -77,3 +84,6 @@ Supported boards:
- MTK mt8173 tablet EVB:
Required root node properties:
- compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
- Evaluation board for MT8183:
Required root node properties:
- compatible = "mediatek,mt8183-evb", "mediatek,mt8183";

98
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
View File

@ -6,6 +6,7 @@
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "mt2712e.dtsi"
/ {
@ -39,6 +40,53 @@
regulator-max-microvolt = <1000000>;
};
extcon_usb: extcon_iddig {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>;
};
extcon_usb1: extcon_iddig1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>;
};
usb_p0_vbus: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "p0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 13 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_p1_vbus: regulator@3 {
compatible = "regulator-fixed";
regulator-name = "p1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_p2_vbus: regulator@4 {
compatible = "regulator-fixed";
regulator-name = "p2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_p3_vbus: regulator@5 {
compatible = "regulator-fixed";
regulator-name = "p3_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
&auxadc {
@ -57,7 +105,57 @@
proc-supply = <&cpus_fixed_vproc1>;
};
&pio {
usb0_id_pins_float: usb0_iddig {
pins_iddig {
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
bias-pull-up;
};
};
usb1_id_pins_float: usb1_iddig {
pins_iddig {
pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
bias-pull-up;
};
};
};
&ssusb {
vbus-supply = <&usb_p0_vbus>;
extcon = <&extcon_usb>;
dr_mode = "otg";
wakeup-source;
mediatek,u3p-dis-msk = <0x1>;
//enable-manual-drd;
//maximum-speed = "full-speed";
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_pins_float>;
status = "okay";
};
&ssusb1 {
vbus-supply = <&usb_p1_vbus>;
extcon = <&extcon_usb1>;
dr_mode = "otg";
//mediatek,u3p-dis-msk = <0x1>;
enable-manual-drd;
wakeup-source;
//maximum-speed = "full-speed";
pinctrl-names = "default";
pinctrl-0 = <&usb1_id_pins_float>;
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_host0 {
vbus-supply = <&usb_p2_vbus>;
status = "okay";
};
&usb_host1 {
status = "okay";
};

555
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View File

@ -8,6 +8,8 @@
#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt2712-larb-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt2712-power.h>
#include "mt2712-pinfunc.h"
@ -312,12 +314,33 @@
status = "disabled";
};
iommu0: iommu@10205000 {
compatible = "mediatek,mt2712-m4u";
reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,larbs = <&larb0 &larb1 &larb2
&larb3 &larb6>;
#iommu-cells = <1>;
};
apmixedsys: syscon@10209000 {
compatible = "mediatek,mt2712-apmixedsys", "syscon";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
iommu1: iommu@1020a000 {
compatible = "mediatek,mt2712-m4u";
reg = <0 0x1020a000 0 0x1000>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,larbs = <&larb4 &larb5 &larb7>;
#iommu-cells = <1>;
};
mcucfg: syscon@10220000 {
compatible = "mediatek,mt2712-mcucfg", "syscon";
reg = <0 0x10220000 0 0x1000>;
@ -395,6 +418,210 @@
status = "disabled";
};
pwm: pwm@11006000 {
compatible = "mediatek,mt2712-pwm";
reg = <0 0x11006000 0 0x1000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_PWM_SEL>,
<&pericfg CLK_PERI_PWM>,
<&pericfg CLK_PERI_PWM0>,
<&pericfg CLK_PERI_PWM1>,
<&pericfg CLK_PERI_PWM2>,
<&pericfg CLK_PERI_PWM3>,
<&pericfg CLK_PERI_PWM4>,
<&pericfg CLK_PERI_PWM5>,
<&pericfg CLK_PERI_PWM6>,
<&pericfg CLK_PERI_PWM7>;
clock-names = "top",
"main",
"pwm1",
"pwm2",
"pwm3",
"pwm4",
"pwm5",
"pwm6",
"pwm7",
"pwm8";
status = "disabled";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x11007000 0 0x90>,
<0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
clock-div = <4>;
clocks = <&pericfg CLK_PERI_I2C0>,
<&pericfg CLK_PERI_AP_DMA>;
clock-names = "main",
"dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x11008000 0 0x90>,
<0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
clock-div = <4>;
clocks = <&pericfg CLK_PERI_I2C1>,
<&pericfg CLK_PERI_AP_DMA>;
clock-names = "main",
"dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11009000 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x11009000 0 0x90>,
<0 0x11000280 0 0x80>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
clock-div = <4>;
clocks = <&pericfg CLK_PERI_I2C2>,
<&pericfg CLK_PERI_AP_DMA>;
clock-names = "main",
"dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@1100a000 {
compatible = "mediatek,mt2712-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&pericfg CLK_PERI_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
nandc: nfi@1100e000 {
compatible = "mediatek,mt2712-nfc";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
clock-names = "nfi_clk", "pad_clk";
ecc-engine = <&bch>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
bch: ecc@1100f000 {
compatible = "mediatek,mt2712-ecc";
reg = <0 0x1100f000 0 0x1000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
clock-names = "nfiecc_clk";
status = "disabled";
};
i2c3: i2c@11010000 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x11010000 0 0x90>,
<0 0x11000300 0 0x80>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
clock-div = <4>;
clocks = <&pericfg CLK_PERI_I2C3>,
<&pericfg CLK_PERI_AP_DMA>;
clock-names = "main",
"dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@11011000 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x11011000 0 0x90>,
<0 0x11000380 0 0x80>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
clock-div = <4>;
clocks = <&pericfg CLK_PERI_I2C4>,
<&pericfg CLK_PERI_AP_DMA>;
clock-names = "main",
"dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@11013000 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x11013000 0 0x90>,
<0 0x11000100 0 0x80>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
clock-div = <4>;
clocks = <&pericfg CLK_PERI_I2C5>,
<&pericfg CLK_PERI_AP_DMA>;
clock-names = "main",
"dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@11015000 {
compatible = "mediatek,mt2712-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11015000 0 0x100>;
interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&pericfg CLK_PERI_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi3: spi@11016000 {
compatible = "mediatek,mt2712-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11016000 0 0x100>;
interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&pericfg CLK_PERI_SPI3>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi4: spi@10012000 {
compatible = "mediatek,mt2712-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x10012000 0 0x100>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_AO_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi5: spi@11018000 {
compatible = "mediatek,mt2712-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11018000 0 0x100>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&pericfg CLK_PERI_SPI5>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
uart4: serial@11019000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
@ -405,6 +632,228 @@
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt2712-mmc";
reg = <0 0x11230000 0 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_0>,
<&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
<&pericfg CLK_PERI_MSDC30_0_QTR_EN>,
<&pericfg CLK_PERI_MSDC50_0_EN>;
clock-names = "source", "hclk", "bus_clk", "source_cg";
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt2712-mmc";
reg = <0 0x11240000 0 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_1>,
<&topckgen CLK_TOP_AXI_SEL>,
<&pericfg CLK_PERI_MSDC30_1_EN>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
mmc2: mmc@11250000 {
compatible = "mediatek,mt2712-mmc";
reg = <0 0x11250000 0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_2>,
<&topckgen CLK_TOP_AXI_SEL>,
<&pericfg CLK_PERI_MSDC30_2_EN>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
ssusb: usb@11271000 {
compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
reg = <0 0x11271000 0 0x3000>,
<0 0x11280700 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
phys = <&u2port0 PHY_TYPE_USB2>,
<&u2port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>;
clock-names = "sys_ck";
mediatek,syscon-wakeup = <&pericfg 0x510 2>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_host0: xhci@11270000 {
compatible = "mediatek,mt2712-xhci",
"mediatek,mtk-xhci";
reg = <0 0x11270000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
clock-names = "sys_ck", "ref_ck";
status = "disabled";
};
};
u3phy0: usb-phy@11290000 {
compatible = "mediatek,mt2712-u3phy";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
u2port0: usb-phy@11290000 {
reg = <0 0x11290000 0 0x700>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u2port1: usb-phy@11298000 {
reg = <0 0x11298000 0 0x700>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u3port0: usb-phy@11298700 {
reg = <0 0x11298700 0 0x900>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
};
ssusb1: usb@112c1000 {
compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
reg = <0 0x112c1000 0 0x3000>,
<0 0x112d0700 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>;
phys = <&u2port2 PHY_TYPE_USB2>,
<&u2port3 PHY_TYPE_USB2>,
<&u3port1 PHY_TYPE_USB3>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
clocks = <&topckgen CLK_TOP_USB30_SEL>;
clock-names = "sys_ck";
mediatek,syscon-wakeup = <&pericfg 0x514 2>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_host1: xhci@112c0000 {
compatible = "mediatek,mt2712-xhci",
"mediatek,mtk-xhci";
reg = <0 0x112c0000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
clock-names = "sys_ck", "ref_ck";
status = "disabled";
};
};
u3phy1: usb-phy@112e0000 {
compatible = "mediatek,mt2712-u3phy";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
u2port2: usb-phy@112e0000 {
reg = <0 0x112e0000 0 0x700>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u2port3: usb-phy@112e8000 {
reg = <0 0x112e8000 0 0x700>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u3port1: usb-phy@112e8700 {
reg = <0 0x112e8700 0 0x900>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
};
pcie: pcie@11700000 {
compatible = "mediatek,mt2712-pcie";
device_type = "pci";
reg = <0 0x11700000 0 0x1000>,
<0 0x112ff000 0 0x1000>;
reg-names = "port0", "port1";
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
<&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
<&pericfg CLK_PERI_PCIE0>,
<&pericfg CLK_PERI_PCIE1>;
clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
phy-names = "pcie-phy0", "pcie-phy1";
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
pcie0: pcie@0,0 {
device_type = "pci";
status = "disabled";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
num-lanes = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@1,0 {
device_type = "pci";
status = "disabled";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
num-lanes = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
mfgcfg: syscon@13000000 {
compatible = "mediatek,mt2712-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
@ -417,12 +866,85 @@
#clock-cells = <1>;
};
larb0: larb@14021000 {
compatible = "mediatek,mt2712-smi-larb";
reg = <0 0x14021000 0 0x1000>;
mediatek,smi = <&smi_common0>;
mediatek,larb-id = <0>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_LARB0>,
<&mmsys CLK_MM_SMI_LARB0>;
clock-names = "apb", "smi";
};
smi_common0: smi@14022000 {
compatible = "mediatek,mt2712-smi-common";
reg = <0 0x14022000 0 0x1000>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>;
clock-names = "apb", "smi";
};
larb4: larb@14027000 {
compatible = "mediatek,mt2712-smi-larb";
reg = <0 0x14027000 0 0x1000>;
mediatek,smi = <&smi_common1>;
mediatek,larb-id = <4>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_LARB4>,
<&mmsys CLK_MM_SMI_LARB4>;
clock-names = "apb", "smi";
};
larb5: larb@14030000 {
compatible = "mediatek,mt2712-smi-larb";
reg = <0 0x14030000 0 0x1000>;
mediatek,smi = <&smi_common1>;
mediatek,larb-id = <5>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_LARB5>,
<&mmsys CLK_MM_SMI_LARB5>;
clock-names = "apb", "smi";
};
smi_common1: smi@14031000 {
compatible = "mediatek,mt2712-smi-common";
reg = <0 0x14031000 0 0x1000>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_COMMON1>,
<&mmsys CLK_MM_SMI_COMMON1>;
clock-names = "apb", "smi";
};
larb7: larb@14032000 {
compatible = "mediatek,mt2712-smi-larb";
reg = <0 0x14032000 0 0x1000>;
mediatek,smi = <&smi_common1>;
mediatek,larb-id = <7>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_LARB7>,
<&mmsys CLK_MM_SMI_LARB7>;
clock-names = "apb", "smi";
};
imgsys: syscon@15000000 {
compatible = "mediatek,mt2712-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
larb2: larb@15001000 {
compatible = "mediatek,mt2712-smi-larb";
reg = <0 0x15001000 0 0x1000>;
mediatek,smi = <&smi_common0>;
mediatek,larb-id = <2>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
clocks = <&imgsys CLK_IMG_SMI_LARB2>,
<&imgsys CLK_IMG_SMI_LARB2>;
clock-names = "apb", "smi";
};
bdpsys: syscon@15010000 {
compatible = "mediatek,mt2712-bdpsys", "syscon";
reg = <0 0x15010000 0 0x1000>;
@ -435,12 +957,45 @@
#clock-cells = <1>;
};
larb1: larb@16010000 {
compatible = "mediatek,mt2712-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common0>;
mediatek,larb-id = <1>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
clocks = <&vdecsys CLK_VDEC_CKEN>,
<&vdecsys CLK_VDEC_LARB1_CKEN>;
clock-names = "apb", "smi";
};
vencsys: syscon@18000000 {
compatible = "mediatek,mt2712-vencsys", "syscon";
reg = <0 0x18000000 0 0x1000>;
#clock-cells = <1>;
};
larb3: larb@18001000 {
compatible = "mediatek,mt2712-smi-larb";
reg = <0 0x18001000 0 0x1000>;
mediatek,smi = <&smi_common0>;
mediatek,larb-id = <3>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
<&vencsys CLK_VENC_VENC>;
clock-names = "apb", "smi";
};
larb6: larb@18002000 {
compatible = "mediatek,mt2712-smi-larb";
reg = <0 0x18002000 0 0x1000>;
mediatek,smi = <&smi_common0>;
mediatek,larb-id = <6>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
<&vencsys CLK_VENC_VENC>;
clock-names = "apb", "smi";
};
jpgdecsys: syscon@19000000 {
compatible = "mediatek,mt2712-jpgdecsys", "syscon";
reg = <0 0x19000000 0 0x1000>;

2
arch/arm64/boot/dts/mediatek/mt6797-evb.dts
View File

@ -33,4 +33,6 @@
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
};

2
arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
View File

@ -30,4 +30,6 @@
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
};

28
arch/arm64/boot/dts/mediatek/mt6797.dtsi
View File

@ -14,6 +14,7 @@
#include <dt-bindings/clock/mt6797-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
/ {
compatible = "mediatek,mt6797";
@ -129,6 +130,33 @@
#clock-cells = <1>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt6797-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x400>,
<0 0x10002400 0 0x400>,
<0 0x10002800 0 0x400>,
<0 0x10002C00 0 0x400>;
reg-names = "gpio", "iocfgl", "iocfgb",
"iocfgr", "iocfgt";
gpio-controller;
#gpio-cells = <2>;
uart0_pins_a: uart0 {
pins0 {
pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
<MT6797_GPIO235__FUNC_URXD0>;
};
};
uart1_pins_a: uart1 {
pins1 {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
};
scpsys: scpsys@10006000 {
compatible = "mediatek,mt6797-scpsys";
#power-domain-cells = <1>;

9
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View File

@ -170,17 +170,20 @@
cooling-maps {
map0 {
trip = <&cpu_passive>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_active>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map2 {
trip = <&cpu_hot>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

6
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View File

@ -276,12 +276,14 @@
cooling-maps {
map@0 {
trip = <&target>;
cooling-device = <&cpu0 0 0>;
cooling-device = <&cpu0 0 0>,
<&cpu1 0 0>;
contribution = <3072>;
};
map@1 {
trip = <&target>;
cooling-device = <&cpu2 0 0>;
cooling-device = <&cpu2 0 0>,
<&cpu3 0 0>;
contribution = <1024>;
};
};