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Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6 

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (110 commits)
  sh: i2c-sh7760: Replase from ctrl_* to __raw_*
  sh: clkfwk: Shuffle around to match the intc split up.
  sh: clkfwk: modify for_each_frequency end condition
  sh: fix clk_get() error handling
  sh: clkfwk: Fix fault in frequency iterator.
  sh: clkfwk: Add a helper for rate rounding by divisor ranges.
  sh: clkfwk: Abstract rate rounding helper.
  sh: clkfwk: support clock remapping.
  sh: pci: Convert to upper/lower_32_bits() helpers.
  sh: mach-sdk7786: Add support for the FPGA SRAM.
  sh: Provide a generic SRAM pool for tiny memories.
  sh: pci: Support secondary FPGA-driven PCIe clocks on SDK7786.
  sh: pci: Support slot 4 routing on SDK7786.
  sh: Fix up PMB locking.
  sh: mach-sdk7786: Add support for fpga gpios.
  sh: use pr_fmt for clock framework, too.
  sh: remove name and id from struct clk
  sh: free-without-alloc fix for sh_mobile_lcdcfb
  sh: perf: Set up perf_max_events.
  sh: perf: Support SH-X3 hardware counters.
  ...

Fix up trivial conflicts (perf_max_events got removed) in arch/sh/kernel/perf_event.c
hifive-unleashed-5.1
Linus Torvalds 2010-10-25 07:51:49 -07:00
parent 8e775167d5 8df399018d
commit 1dfd166e93
168 changed files with 7309 additions and 3100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/sh/Kconfig
View File

@ -24,6 +24,7 @@ config SUPERH
select HAVE_KERNEL_LZMA
select HAVE_KERNEL_LZO
select HAVE_SYSCALL_TRACEPOINTS
select HAVE_REGS_AND_STACK_ACCESS_API
select RTC_LIB
select GENERIC_ATOMIC64
help
@ -46,7 +47,7 @@ config SUPERH32
select HAVE_ARCH_KGDB
select HAVE_HW_BREAKPOINT
select HAVE_MIXED_BREAKPOINTS_REGS
select PERF_EVENTS if HAVE_HW_BREAKPOINT
select PERF_EVENTS
select ARCH_HIBERNATION_POSSIBLE if MMU
config SUPERH64
@ -471,6 +472,7 @@ config CPU_SUBTYPE_SHX3
select CPU_SH4A
select CPU_SHX3
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
select ARCH_REQUIRE_GPIOLIB
# SH4AL-DSP Processor Support
@ -575,7 +577,7 @@ config SH_CLK_CPG
config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
!CPU_SUBTYPE_SH7786
!CPU_SHX3 && !CPU_SUBTYPE_SH7757
config SH_CLK_MD
int "CPU Mode Pin Setting"

18
arch/sh/boards/Kconfig
View File

@ -155,6 +155,8 @@ config SH_SDK7786
depends on CPU_SUBTYPE_SH7786
select SYS_SUPPORTS_PCI
select NO_IOPORT if !PCI
select ARCH_WANT_OPTIONAL_GPIOLIB
select HAVE_SRAM_POOL
help
Select SDK7786 if configuring for a Renesas Technology Europe
SH7786-65nm board.
@ -165,6 +167,11 @@ config SH_HIGHLANDER
select SYS_SUPPORTS_PCI
select IO_TRAPPED if MMU
config SH_SH7757LCR
bool "SH7757LCR"
depends on CPU_SUBTYPE_SH7757
select ARCH_REQUIRE_GPIOLIB
config SH_SH7785LCR
bool "SH7785LCR"
depends on CPU_SUBTYPE_SH7785
@ -309,6 +316,17 @@ config SH_POLARIS
help
Select if configuring for an SMSC Polaris development board
config SH_SH2007
bool "SH-2007 board"
select NO_IOPORT
depends on CPU_SUBTYPE_SH7780
help
SH-2007 is a single-board computer based around SH7780 chip
intended for embedded applications.
It has an Ethernet interface (SMC9118), direct connected
Compact Flash socket, two serial ports and PC-104 bus.
More information at <http://sh2000.sh-linux.org>.
endmenu
source "arch/sh/boards/mach-r2d/Kconfig"

2
arch/sh/boards/Makefile
View File

@ -2,6 +2,7 @@
# Specific board support, not covered by a mach group.
#
obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o
obj-$(CONFIG_SH_SH2007) += board-sh2007.o
obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o
obj-$(CONFIG_SH_URQUELL) += board-urquell.o
obj-$(CONFIG_SH_SHMIN) += board-shmin.o
@ -9,3 +10,4 @@ obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o
obj-$(CONFIG_SH_ESPT) += board-espt.o
obj-$(CONFIG_SH_POLARIS) += board-polaris.o
obj-$(CONFIG_SH_TITAN) += board-titan.o
obj-$(CONFIG_SH_SH7757LCR) += board-sh7757lcr.o

133
arch/sh/boards/board-sh2007.c 100644
View File

@ -0,0 +1,133 @@
/*
* SH-2007 board support.
*
* Copyright (C) 2003, 2004 SUGIOKA Toshinobu
* Copyright (C) 2010 Hitoshi Mitake <mitake@dcl.info.waseda.ac.jp>
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/smsc911x.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/io.h>
#include <asm/machvec.h>
#include <mach/sh2007.h>
struct smsc911x_platform_config smc911x_info = {
.flags = SMSC911X_USE_32BIT,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
};
static struct resource smsc9118_0_resources[] = {
[0] = {
.start = SMC0_BASE,
.end = SMC0_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x240),
.end = evt2irq(0x240),
.flags = IORESOURCE_IRQ,
}
};
static struct resource smsc9118_1_resources[] = {
[0] = {
.start = SMC1_BASE,
.end = SMC1_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x280),
.end = evt2irq(0x280),
.flags = IORESOURCE_IRQ,
}
};
static struct platform_device smsc9118_0_device = {
.name = "smsc911x",
.id = 0,
.num_resources = ARRAY_SIZE(smsc9118_0_resources),
.resource = smsc9118_0_resources,
.dev = {
.platform_data = &smc911x_info,
},
};
static struct platform_device smsc9118_1_device = {
.name = "smsc911x",
.id = 1,
.num_resources = ARRAY_SIZE(smsc9118_1_resources),
.resource = smsc9118_1_resources,
.dev = {
.platform_data = &smc911x_info,
},
};
static struct resource cf_resources[] = {
[0] = {
.start = CF_BASE + CF_OFFSET,
.end = CF_BASE + CF_OFFSET + 0x0f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CF_BASE + CF_OFFSET + 0x206,
.end = CF_BASE + CF_OFFSET + 0x20f,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = evt2irq(0x2c0),
.end = evt2irq(0x2c0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cf_device = {
.name = "pata_platform",
.id = 0,
.num_resources = ARRAY_SIZE(cf_resources),
.resource = cf_resources,
};
static struct platform_device *sh2007_devices[] __initdata = {
&smsc9118_0_device,
&smsc9118_1_device,
&cf_device,
};
static int __init sh2007_io_init(void)
{
platform_add_devices(sh2007_devices, ARRAY_SIZE(sh2007_devices));
return 0;
}
subsys_initcall(sh2007_io_init);
static void __init sh2007_init_irq(void)
{
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
/*
* Initialize the board
*/
static void __init sh2007_setup(char **cmdline_p)
{
printk(KERN_INFO "SH-2007 Setup...");
/* setup wait control registers for area 5 */
__raw_writel(CS5BCR_D, CS5BCR);
__raw_writel(CS5WCR_D, CS5WCR);
__raw_writel(CS5PCR_D, CS5PCR);
printk(KERN_INFO " done.\n");
}
/*
* The Machine Vector
*/
struct sh_machine_vector mv_sh2007 __initmv = {
.mv_setup = sh2007_setup,
.mv_name = "sh2007",
.mv_init_irq = sh2007_init_irq,
};

374
arch/sh/boards/board-sh7757lcr.c 100644
View File

@ -0,0 +1,374 @@
/*
* Renesas R0P7757LC0012RL Support.
*
* Copyright (C) 2009 - 2010 Renesas Solutions Corp.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/io.h>
#include <cpu/sh7757.h>
#include <asm/sh_eth.h>
#include <asm/heartbeat.h>
static struct resource heartbeat_resource = {
.start = 0xffec005c, /* PUDR */
.end = 0xffec005c,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
};
static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
.flags = HEARTBEAT_INVERTED,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* Fast Ethernet */
static struct resource sh_eth0_resources[] = {
{
.start = 0xfef00000,
.end = 0xfef001ff,
.flags = IORESOURCE_MEM,
}, {
.start = 84,
.end = 84,
.flags = IORESOURCE_IRQ,
},
};
static struct sh_eth_plat_data sh7757_eth0_pdata = {
.phy = 1,
.edmac_endian = EDMAC_LITTLE_ENDIAN,
};
static struct platform_device sh7757_eth0_device = {
.name = "sh-eth",
.resource = sh_eth0_resources,
.id = 0,
.num_resources = ARRAY_SIZE(sh_eth0_resources),
.dev = {
.platform_data = &sh7757_eth0_pdata,
},
};
static struct resource sh_eth1_resources[] = {
{
.start = 0xfef00800,
.end = 0xfef009ff,
.flags = IORESOURCE_MEM,
}, {
.start = 84,
.end = 84,
.flags = IORESOURCE_IRQ,
},
};
static struct sh_eth_plat_data sh7757_eth1_pdata = {
.phy = 1,
.edmac_endian = EDMAC_LITTLE_ENDIAN,
};
static struct platform_device sh7757_eth1_device = {
.name = "sh-eth",
.resource = sh_eth1_resources,
.id = 1,
.num_resources = ARRAY_SIZE(sh_eth1_resources),
.dev = {
.platform_data = &sh7757_eth1_pdata,
},
};
static struct platform_device *sh7757lcr_devices[] __initdata = {
&heartbeat_device,
&sh7757_eth0_device,
&sh7757_eth1_device,
};
static int __init sh7757lcr_devices_setup(void)
{
/* RGMII (PTA) */
gpio_request(GPIO_FN_ET0_MDC, NULL);
gpio_request(GPIO_FN_ET0_MDIO, NULL);
gpio_request(GPIO_FN_ET1_MDC, NULL);
gpio_request(GPIO_FN_ET1_MDIO, NULL);
/* ONFI (PTB, PTZ) */
gpio_request(GPIO_FN_ON_NRE, NULL);
gpio_request(GPIO_FN_ON_NWE, NULL);
gpio_request(GPIO_FN_ON_NWP, NULL);
gpio_request(GPIO_FN_ON_NCE0, NULL);
gpio_request(GPIO_FN_ON_R_B0, NULL);
gpio_request(GPIO_FN_ON_ALE, NULL);
gpio_request(GPIO_FN_ON_CLE, NULL);
gpio_request(GPIO_FN_ON_DQ7, NULL);
gpio_request(GPIO_FN_ON_DQ6, NULL);
gpio_request(GPIO_FN_ON_DQ5, NULL);
gpio_request(GPIO_FN_ON_DQ4, NULL);
gpio_request(GPIO_FN_ON_DQ3, NULL);
gpio_request(GPIO_FN_ON_DQ2, NULL);
gpio_request(GPIO_FN_ON_DQ1, NULL);
gpio_request(GPIO_FN_ON_DQ0, NULL);
/* IRQ8 to 0 (PTB, PTC) */
gpio_request(GPIO_FN_IRQ8, NULL);
gpio_request(GPIO_FN_IRQ7, NULL);
gpio_request(GPIO_FN_IRQ6, NULL);
gpio_request(GPIO_FN_IRQ5, NULL);
gpio_request(GPIO_FN_IRQ4, NULL);
gpio_request(GPIO_FN_IRQ3, NULL);
gpio_request(GPIO_FN_IRQ2, NULL);
gpio_request(GPIO_FN_IRQ1, NULL);
gpio_request(GPIO_FN_IRQ0, NULL);
/* SPI0 (PTD) */
gpio_request(GPIO_FN_SP0_MOSI, NULL);
gpio_request(GPIO_FN_SP0_MISO, NULL);
gpio_request(GPIO_FN_SP0_SCK, NULL);
gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
gpio_request(GPIO_FN_SP0_SS0, NULL);
gpio_request(GPIO_FN_SP0_SS1, NULL);
gpio_request(GPIO_FN_SP0_SS2, NULL);
gpio_request(GPIO_FN_SP0_SS3, NULL);
/* RMII 0/1 (PTE, PTF) */
gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
gpio_request(GPIO_FN_RMII0_TXD1, NULL);
gpio_request(GPIO_FN_RMII0_TXD0, NULL);
gpio_request(GPIO_FN_RMII0_TXEN, NULL);
gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
gpio_request(GPIO_FN_RMII0_RXD1, NULL);
gpio_request(GPIO_FN_RMII0_RXD0, NULL);
gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
gpio_request(GPIO_FN_RMII1_TXD1, NULL);
gpio_request(GPIO_FN_RMII1_TXD0, NULL);
gpio_request(GPIO_FN_RMII1_TXEN, NULL);
gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
gpio_request(GPIO_FN_RMII1_RXD1, NULL);
gpio_request(GPIO_FN_RMII1_RXD0, NULL);
gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
/* eMMC (PTG) */
gpio_request(GPIO_FN_MMCCLK, NULL);
gpio_request(GPIO_FN_MMCCMD, NULL);
gpio_request(GPIO_FN_MMCDAT7, NULL);
gpio_request(GPIO_FN_MMCDAT6, NULL);
gpio_request(GPIO_FN_MMCDAT5, NULL);
gpio_request(GPIO_FN_MMCDAT4, NULL);
gpio_request(GPIO_FN_MMCDAT3, NULL);
gpio_request(GPIO_FN_MMCDAT2, NULL);
gpio_request(GPIO_FN_MMCDAT1, NULL);
gpio_request(GPIO_FN_MMCDAT0, NULL);
/* LPC (PTG, PTH, PTQ, PTU) */
gpio_request(GPIO_FN_SERIRQ, NULL);
gpio_request(GPIO_FN_LPCPD, NULL);
gpio_request(GPIO_FN_LDRQ, NULL);
gpio_request(GPIO_FN_WP, NULL);
gpio_request(GPIO_FN_FMS0, NULL);
gpio_request(GPIO_FN_LAD3, NULL);
gpio_request(GPIO_FN_LAD2, NULL);
gpio_request(GPIO_FN_LAD1, NULL);
gpio_request(GPIO_FN_LAD0, NULL);
gpio_request(GPIO_FN_LFRAME, NULL);
gpio_request(GPIO_FN_LRESET, NULL);
gpio_request(GPIO_FN_LCLK, NULL);
gpio_request(GPIO_FN_LGPIO7, NULL);
gpio_request(GPIO_FN_LGPIO6, NULL);
gpio_request(GPIO_FN_LGPIO5, NULL);
gpio_request(GPIO_FN_LGPIO4, NULL);
/* SPI1 (PTH) */
gpio_request(GPIO_FN_SP1_MOSI, NULL);
gpio_request(GPIO_FN_SP1_MISO, NULL);
gpio_request(GPIO_FN_SP1_SCK, NULL);
gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
gpio_request(GPIO_FN_SP1_SS0, NULL);
gpio_request(GPIO_FN_SP1_SS1, NULL);
/* SDHI (PTI) */
gpio_request(GPIO_FN_SD_WP, NULL);
gpio_request(GPIO_FN_SD_CD, NULL);
gpio_request(GPIO_FN_SD_CLK, NULL);
gpio_request(GPIO_FN_SD_CMD, NULL);
gpio_request(GPIO_FN_SD_D3, NULL);
gpio_request(GPIO_FN_SD_D2, NULL);
gpio_request(GPIO_FN_SD_D1, NULL);
gpio_request(GPIO_FN_SD_D0, NULL);
/* SCIF3/4 (PTJ, PTW) */
gpio_request(GPIO_FN_RTS3, NULL);
gpio_request(GPIO_FN_CTS3, NULL);
gpio_request(GPIO_FN_TXD3, NULL);
gpio_request(GPIO_FN_RXD3, NULL);
gpio_request(GPIO_FN_RTS4, NULL);
gpio_request(GPIO_FN_RXD4, NULL);
gpio_request(GPIO_FN_TXD4, NULL);
gpio_request(GPIO_FN_CTS4, NULL);
/* SERMUX (PTK, PTL, PTO, PTV) */
gpio_request(GPIO_FN_COM2_TXD, NULL);
gpio_request(GPIO_FN_COM2_RXD, NULL);
gpio_request(GPIO_FN_COM2_RTS, NULL);
gpio_request(GPIO_FN_COM2_CTS, NULL);
gpio_request(GPIO_FN_COM2_DTR, NULL);
gpio_request(GPIO_FN_COM2_DSR, NULL);
gpio_request(GPIO_FN_COM2_DCD, NULL);
gpio_request(GPIO_FN_COM2_RI, NULL);
gpio_request(GPIO_FN_RAC_RXD, NULL);
gpio_request(GPIO_FN_RAC_RTS, NULL);
gpio_request(GPIO_FN_RAC_CTS, NULL);
gpio_request(GPIO_FN_RAC_DTR, NULL);
gpio_request(GPIO_FN_RAC_DSR, NULL);
gpio_request(GPIO_FN_RAC_DCD, NULL);
gpio_request(GPIO_FN_RAC_TXD, NULL);
gpio_request(GPIO_FN_COM1_TXD, NULL);
gpio_request(GPIO_FN_COM1_RXD, NULL);
gpio_request(GPIO_FN_COM1_RTS, NULL);
gpio_request(GPIO_FN_COM1_CTS, NULL);
writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */
/* IIC (PTM, PTR, PTS) */
gpio_request(GPIO_FN_SDA7, NULL);
gpio_request(GPIO_FN_SCL7, NULL);
gpio_request(GPIO_FN_SDA6, NULL);
gpio_request(GPIO_FN_SCL6, NULL);
gpio_request(GPIO_FN_SDA5, NULL);
gpio_request(GPIO_FN_SCL5, NULL);
gpio_request(GPIO_FN_SDA4, NULL);
gpio_request(GPIO_FN_SCL4, NULL);
gpio_request(GPIO_FN_SDA3, NULL);
gpio_request(GPIO_FN_SCL3, NULL);
gpio_request(GPIO_FN_SDA2, NULL);
gpio_request(GPIO_FN_SCL2, NULL);
gpio_request(GPIO_FN_SDA1, NULL);
gpio_request(GPIO_FN_SCL1, NULL);
gpio_request(GPIO_FN_SDA0, NULL);
gpio_request(GPIO_FN_SCL0, NULL);
/* USB (PTN) */
gpio_request(GPIO_FN_VBUS_EN, NULL);
gpio_request(GPIO_FN_VBUS_OC, NULL);
/* SGPIO1/0 (PTN, PTO) */
gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
gpio_request(GPIO_FN_SGPIO1_DI, NULL);
gpio_request(GPIO_FN_SGPIO1_DO, NULL);
gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
gpio_request(GPIO_FN_SGPIO0_DI, NULL);
gpio_request(GPIO_FN_SGPIO0_DO, NULL);
/* WDT (PTN) */
gpio_request(GPIO_FN_SUB_CLKIN, NULL);
/* System (PTT) */
gpio_request(GPIO_FN_STATUS1, NULL);
gpio_request(GPIO_FN_STATUS0, NULL);
/* PWMX (PTT) */
gpio_request(GPIO_FN_PWMX1, NULL);
gpio_request(GPIO_FN_PWMX0, NULL);
/* R-SPI (PTV) */
gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
gpio_request(GPIO_FN_R_SPI_MISO, NULL);
gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
/* EVC (PTV, PTW) */
gpio_request(GPIO_FN_EVENT7, NULL);
gpio_request(GPIO_FN_EVENT6, NULL);
gpio_request(GPIO_FN_EVENT5, NULL);
gpio_request(GPIO_FN_EVENT4, NULL);
gpio_request(GPIO_FN_EVENT3, NULL);
gpio_request(GPIO_FN_EVENT2, NULL);
gpio_request(GPIO_FN_EVENT1, NULL);
gpio_request(GPIO_FN_EVENT0, NULL);
/* LED for heartbeat */
gpio_request(GPIO_PTU3, NULL);
gpio_direction_output(GPIO_PTU3, 1);
gpio_request(GPIO_PTU2, NULL);
gpio_direction_output(GPIO_PTU2, 1);
gpio_request(GPIO_PTU1, NULL);
gpio_direction_output(GPIO_PTU1, 1);
gpio_request(GPIO_PTU0, NULL);
gpio_direction_output(GPIO_PTU0, 1);
/* control for MDIO of Gigabit Ethernet */
gpio_request(GPIO_PTT4, NULL);
gpio_direction_output(GPIO_PTT4, 1);
/* control for eMMC */
gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */
gpio_direction_output(GPIO_PTT7, 0);
gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */
gpio_direction_output(GPIO_PTT6, 0);
gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */
gpio_direction_output(GPIO_PTT5, 1);
/* General platform */
return platform_add_devices(sh7757lcr_devices,
ARRAY_SIZE(sh7757lcr_devices));
}
arch_initcall(sh7757lcr_devices_setup);
/* Initialize IRQ setting */
void __init init_sh7757lcr_IRQ(void)
{
plat_irq_setup_pins(IRQ_MODE_IRQ7654);
plat_irq_setup_pins(IRQ_MODE_IRQ3210);
}
/* Initialize the board */
static void __init sh7757lcr_setup(char **cmdline_p)
{
printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
}
static int sh7757lcr_mode_pins(void)
{
int value = 0;
/* These are the factory default settings of S3 (Low active).
* If you change these dip switches then you will need to
* adjust the values below as well.
*/
value |= MODE_PIN0; /* Clock Mode: 1 */
return value;
}
/* The Machine Vector */
static struct sh_machine_vector mv_sh7757lcr __initmv = {
.mv_name = "SH7757LCR",
.mv_setup = sh7757lcr_setup,
.mv_init_irq = init_sh7757lcr_IRQ,
.mv_mode_pins = sh7757lcr_mode_pins,
};

6
arch/sh/boards/mach-ecovec24/setup.c
View File

@ -1248,14 +1248,14 @@ static int __init arch_setup(void)
/* set SPU2 clock to 83.4 MHz */
clk = clk_get(NULL, "spu_clk");
if (clk) {
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 83333333));
clk_put(clk);
}
/* change parent of FSI B */
clk = clk_get(NULL, "fsib_clk");
if (clk) {
if (!IS_ERR(clk)) {
clk_register(&fsimckb_clk);
clk_set_parent(clk, &fsimckb_clk);
clk_set_rate(clk, 11000);
@ -1273,7 +1273,7 @@ static int __init arch_setup(void)
/* set VPU clock to 166 MHz */
clk = clk_get(NULL, "vpu_clk");
if (clk) {
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 166000000));
clk_put(clk);
}

5
arch/sh/boards/mach-sdk7786/Makefile
View File

@ -1 +1,4 @@
obj-y := setup.o fpga.o irq.o
obj-y := fpga.o irq.o setup.o
obj-$(CONFIG_GENERIC_GPIO) += gpio.o
obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o

49
arch/sh/boards/mach-sdk7786/gpio.c 100644
View File

@ -0,0 +1,49 @@
/*
* SDK7786 FPGA USRGPIR Support.
*
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <mach/fpga.h>
#define NR_FPGA_GPIOS 8
static const char *usrgpir_gpio_names[NR_FPGA_GPIOS] = {
"in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7",
};
static int usrgpir_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
/* always in */
return 0;
}
static int usrgpir_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
return !!(fpga_read_reg(USRGPIR) & (1 << gpio));
}
static struct gpio_chip usrgpir_gpio_chip = {
.label = "sdk7786-fpga",
.names = usrgpir_gpio_names,
.direction_input = usrgpir_gpio_direction_input,
.get = usrgpir_gpio_get,
.base = -1, /* don't care */
.ngpio = NR_FPGA_GPIOS,
};
static int __init usrgpir_gpio_setup(void)
{
return gpiochip_add(&usrgpir_gpio_chip);
}
device_initcall(usrgpir_gpio_setup);

54
arch/sh/boards/mach-sdk7786/setup.c
View File

@ -20,6 +20,8 @@
#include <asm/machvec.h>
#include <asm/heartbeat.h>
#include <asm/sizes.h>
#include <asm/clock.h>
#include <asm/clkdev.h>
#include <asm/reboot.h>
#include <asm/smp-ops.h>
@ -140,6 +142,45 @@ static int sdk7786_mode_pins(void)
return fpga_read_reg(MODSWR);
}
/*
* FPGA-driven PCIe clocks
*
* Historically these include the oscillator, clock B (slots 2/3/4) and
* clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
* everything under a single PCIe clocks enable bit that happens to map
* to the same bit position as the oscillator bit for earlier FPGA
* versions.
*
* Given that the legacy clocks have the side-effect of shutting the CPU
* off through the FPGA along with the PCI slots, we simply leave them in
* their initial state and don't bother registering them with the clock
* framework.
*/
static int sdk7786_pcie_clk_enable(struct clk *clk)
{
fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
return 0;
}
static void sdk7786_pcie_clk_disable(struct clk *clk)
{
fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
}
static struct clk_ops sdk7786_pcie_clk_ops = {
.enable = sdk7786_pcie_clk_enable,
.disable = sdk7786_pcie_clk_disable,
};
static struct clk sdk7786_pcie_clk = {
.ops = &sdk7786_pcie_clk_ops,
};
static struct clk_lookup sdk7786_pcie_cl = {
.con_id = "pcie_plat_clk",
.clk = &sdk7786_pcie_clk,
};
static int sdk7786_clk_init(void)
{
struct clk *clk;
@ -158,7 +199,18 @@ static int sdk7786_clk_init(void)
ret = clk_set_rate(clk, 33333333);
clk_put(clk);
return ret;
/*
* Setup the FPGA clocks.
*/
ret = clk_register(&sdk7786_pcie_clk);
if (unlikely(ret)) {
pr_err("FPGA clock registration failed\n");
return ret;
}
clkdev_add(&sdk7786_pcie_cl);
return 0;
}
static void sdk7786_restart(char *cmd)

72
arch/sh/boards/mach-sdk7786/sram.c 100644
View File

@ -0,0 +1,72 @@
/*
* SDK7786 FPGA SRAM Support.
*
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/string.h>
#include <mach/fpga.h>
#include <asm/sram.h>
#include <asm/sizes.h>
static int __init fpga_sram_init(void)
{
unsigned long phys;
unsigned int area;
void __iomem *vaddr;
int ret;
u16 data;
/* Enable FPGA SRAM */
data = fpga_read_reg(LCLASR);
data |= LCLASR_FRAMEN;
fpga_write_reg(data, LCLASR);
/*
* FPGA_SEL determines the area mapping
*/
area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT;
if (unlikely(area == LCLASR_AREA_MASK)) {
pr_err("FPGA memory unmapped.\n");
return -ENXIO;
}
/*
* The memory itself occupies a 2KiB range at the top of the area
* immediately below the system registers.
*/
phys = (area << 26) + SZ_64M - SZ_4K;
/*
* The FPGA SRAM resides in translatable physical space, so set
* up a mapping prior to inserting it in to the pool.
*/
vaddr = ioremap(phys, SZ_2K);
if (unlikely(!vaddr)) {
pr_err("Failed remapping FPGA memory.\n");
return -ENXIO;
}
pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx "
"(area %d) to pool.\n",
SZ_2K >> 10, phys, phys + SZ_2K - 1, area);
ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1);
if (unlikely(ret < 0)) {
pr_err("Failed adding memory\n");
iounmap(vaddr);
return ret;
}
return 0;
}
postcore_initcall(fpga_sram_init);

2
arch/sh/boards/mach-x3proto/Makefile
View File

@ -1 +1,3 @@
obj-y += setup.o ilsel.o
obj-$(CONFIG_GENERIC_GPIO) += gpio.o

135
arch/sh/boards/mach-x3proto/gpio.c 100644
View File

@ -0,0 +1,135 @@
/*
* arch/sh/boards/mach-x3proto/gpio.c
*
* Renesas SH-X3 Prototype Baseboard GPIO Support.
*
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <mach/ilsel.h>
#include <mach/hardware.h>
#define KEYCTLR 0xb81c0000
#define KEYOUTR 0xb81c0002
#define KEYDETR 0xb81c0004
static DEFINE_SPINLOCK(x3proto_gpio_lock);
static unsigned int x3proto_gpio_irq_map[NR_BASEBOARD_GPIOS] = { 0, };
static int x3proto_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
unsigned long flags;
unsigned int data;
spin_lock_irqsave(&x3proto_gpio_lock, flags);
data = __raw_readw(KEYCTLR);
data |= (1 << gpio);
__raw_writew(data, KEYCTLR);
spin_unlock_irqrestore(&x3proto_gpio_lock, flags);
return 0;
}
static int x3proto_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
return !!(__raw_readw(KEYDETR) & (1 << gpio));
}
static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
{
return x3proto_gpio_irq_map[gpio];
}
static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
unsigned long mask;
int pin;
chip->mask_ack(irq);
mask = __raw_readw(KEYDETR);
for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS)
generic_handle_irq(x3proto_gpio_to_irq(NULL, pin));
chip->unmask(irq);
}
struct gpio_chip x3proto_gpio_chip = {
.label = "x3proto-gpio",
.direction_input = x3proto_gpio_direction_input,
.get = x3proto_gpio_get,
.to_irq = x3proto_gpio_to_irq,
.base = -1,
.ngpio = NR_BASEBOARD_GPIOS,
};
int __init x3proto_gpio_setup(void)
{
int ilsel;
int ret, i;
ilsel = ilsel_enable(ILSEL_KEY);
if (unlikely(ilsel < 0))
return ilsel;
ret = gpiochip_add(&x3proto_gpio_chip);
if (unlikely(ret))
goto err_gpio;
for (i = 0; i < NR_BASEBOARD_GPIOS; i++) {
unsigned long flags;
int irq = create_irq();
if (unlikely(irq < 0)) {
ret = -EINVAL;
goto err_irq;
}
spin_lock_irqsave(&x3proto_gpio_lock, flags);
x3proto_gpio_irq_map[i] = irq;
set_irq_chip_and_handler_name(irq, &dummy_irq_chip,
handle_simple_irq, "gpio");
spin_unlock_irqrestore(&x3proto_gpio_lock, flags);
}
pr_info("registering '%s' support, handling GPIOs %u -> %u, "
"bound to IRQ %u\n",
x3proto_gpio_chip.label, x3proto_gpio_chip.base,
x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio,
ilsel);
set_irq_chained_handler(ilsel, x3proto_gpio_irq_handler);
set_irq_wake(ilsel, 1);
return 0;
err_irq:
for (; i >= 0; --i)
if (x3proto_gpio_irq_map[i])
destroy_irq(x3proto_gpio_irq_map[i]);
ret = gpiochip_remove(&x3proto_gpio_chip);
if (unlikely(ret))
pr_err("Failed deregistering GPIO\n");
err_gpio:
synchronize_irq(ilsel);
ilsel_disable(ILSEL_KEY);
return ret;
}

18
arch/sh/boards/mach-x3proto/ilsel.c
View File

@ -1,20 +1,22 @@
/*
* arch/sh/boards/renesas/x3proto/ilsel.c
* arch/sh/boards/mach-x3proto/ilsel.c
*
* Helper routines for SH-X3 proto board ILSEL.
*
* Copyright (C) 2007 Paul Mundt
* Copyright (C) 2007 - 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/bitmap.h>
#include <linux/io.h>
#include <asm/ilsel.h>
#include <mach/ilsel.h>
/*
* ILSEL is split across:
@ -64,6 +66,8 @@ static void __ilsel_enable(ilsel_source_t set, unsigned int bit)
unsigned int tmp, shift;
unsigned long addr;
pr_notice("enabling ILSEL set %d\n", set);
addr = mk_ilsel_addr(bit);
shift = mk_ilsel_shift(bit);
@ -92,8 +96,10 @@ int ilsel_enable(ilsel_source_t set)
{
unsigned int bit;
/* Aliased sources must use ilsel_enable_fixed() */
BUG_ON(set > ILSEL_KEY);
if (unlikely(set > ILSEL_KEY)) {
pr_err("Aliased sources must use ilsel_enable_fixed()\n");
return -EINVAL;
}
do {
bit = find_first_zero_bit(&ilsel_level_map, ILSEL_LEVELS);
@ -140,6 +146,8 @@ void ilsel_disable(unsigned int irq)
unsigned long addr;
unsigned int tmp;
pr_notice("disabling ILSEL set %d\n", irq);
addr = mk_ilsel_addr(irq);
tmp = __raw_readw(addr);

132
arch/sh/boards/mach-x3proto/setup.c
View File

@ -1,9 +1,9 @@
/*
* arch/sh/boards/renesas/x3proto/setup.c
* arch/sh/boards/mach-x3proto/setup.c
*
* Renesas SH-X3 Prototype Board Support.
*
* Copyright (C) 2007 - 2008 Paul Mundt
* Copyright (C) 2007 - 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
@ -16,9 +16,13 @@
#include <linux/smc91x.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/usb/r8a66597.h>
#include <linux/usb/m66592.h>
#include <asm/ilsel.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <mach/ilsel.h>
#include <mach/hardware.h>
#include <asm/smp-ops.h>
static struct resource heartbeat_resources[] = {
@ -122,15 +126,128 @@ static struct platform_device m66592_usb_peripheral_device = {
.resource = m66592_usb_peripheral_resources,
};
static struct gpio_keys_button baseboard_buttons[NR_BASEBOARD_GPIOS] = {
{
.desc = "key44",
.code = KEY_POWER,
.active_low = 1,
.wakeup = 1,
}, {
.desc = "key43",
.code = KEY_SUSPEND,
.active_low = 1,
.wakeup = 1,
}, {
.desc = "key42",
.code = KEY_KATAKANAHIRAGANA,
.active_low = 1,
}, {
.desc = "key41",
.code = KEY_SWITCHVIDEOMODE,
.active_low = 1,
}, {
.desc = "key34",
.code = KEY_F12,
.active_low = 1,
}, {
.desc = "key33",
.code = KEY_F11,
.active_low = 1,
}, {
.desc = "key32",
.code = KEY_F10,
.active_low = 1,
}, {
.desc = "key31",
.code = KEY_F9,
.active_low = 1,
}, {
.desc = "key24",
.code = KEY_F8,
.active_low = 1,
}, {
.desc = "key23",
.code = KEY_F7,
.active_low = 1,
}, {
.desc = "key22",
.code = KEY_F6,
.active_low = 1,
}, {
.desc = "key21",
.code = KEY_F5,
.active_low = 1,
}, {
.desc = "key14",
.code = KEY_F4,
.active_low = 1,
}, {
.desc = "key13",
.code = KEY_F3,
.active_low = 1,
}, {
.desc = "key12",
.code = KEY_F2,
.active_low = 1,
}, {
.desc = "key11",
.code = KEY_F1,
.active_low = 1,
},
};
static struct gpio_keys_platform_data baseboard_buttons_data = {
.buttons = baseboard_buttons,
.nbuttons = ARRAY_SIZE(baseboard_buttons),
};
static struct platform_device baseboard_buttons_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &baseboard_buttons_data,
},
};
static struct platform_device *x3proto_devices[] __initdata = {
&heartbeat_device,
&smc91x_device,
&r8a66597_usb_host_device,
&m66592_usb_peripheral_device,
&baseboard_buttons_device,
};
static void __init x3proto_init_irq(void)
{
plat_irq_setup_pins(IRQ_MODE_IRL3210);
/* Set ICR0.LVLMODE */
__raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000);
}
static int __init x3proto_devices_setup(void)
{
int ret, i;
/*
* IRLs are only needed for ILSEL mappings, so flip over the INTC
* pins at a later point to enable the GPIOs to settle.
*/
x3proto_init_irq();
/*
* Now that ILSELs are available, set up the baseboard GPIOs.
*/
ret = x3proto_gpio_setup();
if (unlikely(ret))
return ret;
/*
* Propagate dynamic GPIOs for the baseboard button device.
*/
for (i = 0; i < ARRAY_SIZE(baseboard_buttons); i++)
baseboard_buttons[i].gpio = x3proto_gpio_chip.base + i;
r8a66597_usb_host_resources[1].start =
r8a66597_usb_host_resources[1].end = ilsel_enable(ILSEL_USBH_I);
@ -145,14 +262,6 @@ static int __init x3proto_devices_setup(void)
}
device_initcall(x3proto_devices_setup);
static void __init x3proto_init_irq(void)
{
plat_irq_setup_pins(IRQ_MODE_IRL3210);
/* Set ICR0.LVLMODE */
__raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000);
}
static void __init x3proto_setup(char **cmdline_p)
{
register_smp_ops(&shx3_smp_ops);
@ -161,5 +270,4 @@ static void __init x3proto_setup(char **cmdline_p)
static struct sh_machine_vector mv_x3proto __initmv = {
.mv_name = "x3proto",
.mv_setup = x3proto_setup,
.mv_init_irq = x3proto_init_irq,
};

4
arch/sh/boot/compressed/head_32.S
View File

@ -91,7 +91,9 @@ bss_start_addr:
end_addr:
.long _end
init_sr:
.long 0x400000F0 /* Privileged mode, Bank=0, Block=0, IMASK=0xF */
.long 0x500000F0 /* Privileged mode, Bank=0, Block=1, IMASK=0xF */
kexec_magic:
.long 0x400000F0 /* magic used by kexec to parse zImage format */
init_stack_addr:
.long stack_start
decompress_kernel_addr:

2
arch/sh/cchips/hd6446x/Makefile
View File

@ -1,3 +1,3 @@
obj-$(CONFIG_HD64461) += hd64461.o
EXTRA_CFLAGS += -Werror
ccflags-y := -Werror

1
arch/sh/configs/ap325rxa_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_KALLSYMS is not set
CONFIG_SLAB=y
CONFIG_MODULES=y

1
arch/sh/configs/cayman_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_EXPERIMENTAL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SLAB=y
CONFIG_MODULES=y

1
arch/sh/configs/dreamcast_defconfig
View File

@ -2,7 +2,6 @@ CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_SLAB=y
CONFIG_PROFILING=y

1
arch/sh/configs/ecovec24-romimage_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_KALLSYMS is not set
CONFIG_SLAB=y

1
arch/sh/configs/edosk7760_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y

1
arch/sh/configs/espt_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_IPC_NS=y

1
arch/sh/configs/hp6xx_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_SLAB=y

1
arch/sh/configs/kfr2r09-romimage_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_KALLSYMS is not set
CONFIG_SLAB=y

1
arch/sh/configs/kfr2r09_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_KALLSYMS is not set
CONFIG_SLAB=y

1
arch/sh/configs/landisk_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_SLAB=y

1
arch/sh/configs/lboxre2_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_SLAB=y

1
arch/sh/configs/magicpanelr2_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_AUDIT=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set

1
arch/sh/configs/microdev_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_EXPERIMENTAL=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set

1
arch/sh/configs/migor_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set

1
arch/sh/configs/polaris_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_AUDIT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SLAB=y
CONFIG_MODULES=y

1
arch/sh/configs/r7780mp_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set

1
arch/sh/configs/r7785rp_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_RCU_TRACE=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_SLAB=y
CONFIG_PROFILING=y

1
arch/sh/configs/rts7751r2d1_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_SLAB=y

1
arch/sh/configs/rts7751r2dplus_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_SLAB=y

1
arch/sh/configs/sdk7780_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=18
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y

1
arch/sh/configs/se7343_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set

1
arch/sh/configs/se7712_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_KALLSYMS_ALL=y
# CONFIG_BUG is not set

1
arch/sh/configs/se7721_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_KALLSYMS_ALL=y
# CONFIG_BUG is not set

1
arch/sh/configs/se7722_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_PROFILING=y
CONFIG_MODULES=y

1
arch/sh/configs/se7724_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_KALLSYMS is not set
CONFIG_SLAB=y
CONFIG_MODULES=y

1
arch/sh/configs/se7750_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_HOTPLUG is not set

1
arch/sh/configs/se7751_defconfig
View File

@ -2,7 +2,6 @@ CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set

1
arch/sh/configs/se7780_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_KALLSYMS is not set
# CONFIG_HOTPLUG is not set
# CONFIG_EPOLL is not set

1
arch/sh/configs/sh03_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_SLAB=y

212
arch/sh/configs/sh2007_defconfig 100644
View File

@ -0,0 +1,212 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_AUDIT=y
CONFIG_AUDITSYSCALL=y
CONFIG_IKCONFIG=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_SLAB=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_CPU_SUBTYPE_SH7780=y
CONFIG_MEMORY_SIZE=0x08000000
# CONFIG_VSYSCALL is not set
CONFIG_FLATMEM_MANUAL=y
CONFIG_SH_SH2007=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SH_DMA=y
CONFIG_SH_DMA_API=y
CONFIG_NR_DMA_CHANNELS_BOOL=y
CONFIG_HZ_100=y
CONFIG_CMDLINE_OVERWRITE=y
CONFIG_CMDLINE="console=ttySC1,115200 ip=dhcp root=/dev/nfs rw nfsroot=/nfs/rootfs,rsize=1024,wsize=1024 earlyprintk=sh-sci.1"
CONFIG_PCCARD=y
CONFIG_BINFMT_MISC=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_NET_KEY=y
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_NET_IPIP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PKTGEN=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_CDROM_PKTCDVD=y
# CONFIG_MISC_DEVICES is not set
CONFIG_RAID_ATTRS=y
CONFIG_SCSI=y
CONFIG_SCSI_TGT=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_SCSI_SPI_ATTRS=y
CONFIG_SCSI_FC_ATTRS=y
CONFIG_SCSI_ISCSI_ATTRS=y
CONFIG_SCSI_SRP_ATTRS=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_EQUALIZER=y
CONFIG_TUN=y
CONFIG_VETH=y
CONFIG_NET_ETHERNET=y
CONFIG_SMSC911X=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_SH_WDT=y
CONFIG_SSB=y
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_MON=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_DMADEVICES=y
CONFIG_TIMB_DMA=y
CONFIG_EXT3_FS=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=932
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CONFIGFS_FS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=y
CONFIG_NLS_CODEPAGE_775=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=y
CONFIG_NLS_CODEPAGE_855=y
CONFIG_NLS_CODEPAGE_857=y
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
CONFIG_NLS_CODEPAGE_864=y
CONFIG_NLS_CODEPAGE_865=y
CONFIG_NLS_CODEPAGE_866=y
CONFIG_NLS_CODEPAGE_869=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_CODEPAGE_932=y
CONFIG_NLS_CODEPAGE_949=y
CONFIG_NLS_CODEPAGE_874=y
CONFIG_NLS_ISO8859_8=y
CONFIG_NLS_CODEPAGE_1250=y
CONFIG_NLS_CODEPAGE_1251=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=y
CONFIG_NLS_ISO8859_4=y
CONFIG_NLS_ISO8859_5=y
CONFIG_NLS_ISO8859_6=y
CONFIG_NLS_ISO8859_7=y
CONFIG_NLS_ISO8859_9=y
CONFIG_NLS_ISO8859_13=y
CONFIG_NLS_ISO8859_14=y
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=y
CONFIG_NLS_UTF8=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_SCHED_DEBUG is not set
CONFIG_DEBUG_INFO=y
CONFIG_FRAME_POINTER=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SH_STANDARD_BIOS=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_TGR192=y
CONFIG_CRYPTO_WP512=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_LIBCRC32C=y

1
arch/sh/configs/sh7710voipgw_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set

85
arch/sh/configs/sh7757lcr_defconfig 100644
View File

@ -0,0 +1,85 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_CPU_SUBTYPE_SH7757=y
CONFIG_MEMORY_START=0x40000000
CONFIG_MEMORY_SIZE=0x0f000000
CONFIG_PMB=y
CONFIG_FLATMEM_MANUAL=y
CONFIG_SH_SH7757LCR=y
CONFIG_HEARTBEAT=y
CONFIG_SECCOMP=y
CONFIG_CMDLINE_OVERWRITE=y
CONFIG_CMDLINE="console=ttySC2,115200 root=/dev/nfs ip=dhcp"
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_BLK_DEV_RAM=y
# CONFIG_MISC_DEVICES is not set
CONFIG_NETDEVICES=y
CONFIG_PHYLIB=y
CONFIG_VITESSE_PHY=y
CONFIG_MDIO_BITBANG=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_MOUSE_PS2 is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=3
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_INOTIFY=y
CONFIG_ISO9660_FS=y
CONFIG_VFAT_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_SQUASHFS=y
CONFIG_MINIX_FS=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_932=y
CONFIG_NLS_ISO8859_1=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_FTRACE is not set
# CONFIG_CRYPTO_ANSI_CPRNG is not set

1
arch/sh/configs/sh7763rdp_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_IPC_NS=y

1
arch/sh/configs/sh7785lcr_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_SLAB=y
CONFIG_PROFILING=y
CONFIG_MODULES=y

1
arch/sh/configs/shx3_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_MEM_RES_CTLR=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y

1
arch/sh/configs/snapgear_defconfig
View File

@ -1,7 +1,6 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_HOTPLUG is not set

1
arch/sh/configs/systemh_defconfig
View File

@ -1,6 +1,5 @@
CONFIG_EXPERIMENTAL=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set

1
arch/sh/configs/titan_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set

1
arch/sh/configs/ul2_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_PROFILING=y
CONFIG_MODULES=y

4
arch/sh/drivers/dma/dma-api.c
View File

@ -412,8 +412,8 @@ EXPORT_SYMBOL(unregister_dmac);
static int __init dma_api_init(void)
{
printk(KERN_NOTICE "DMA: Registering DMA API.\n");
create_proc_read_entry("dma", 0, 0, dma_read_proc, 0);
return 0;
return create_proc_read_entry("dma", 0, 0, dma_read_proc, 0)
? 0 : -ENOMEM;
}
subsys_initcall(dma_api_init);

1
arch/sh/drivers/pci/Makefile
View File

@ -19,6 +19,7 @@ obj-$(CONFIG_SH_RTS7751R2D) += fixups-rts7751r2d.o
obj-$(CONFIG_SH_SH03) += fixups-sh03.o
obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o
obj-$(CONFIG_SH_SH7785LCR) += fixups-r7780rp.o
obj-$(CONFIG_SH_SDK7786) += fixups-sdk7786.o
obj-$(CONFIG_SH_SDK7780) += fixups-sdk7780.o
obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += fixups-sdk7780.o
obj-$(CONFIG_SH_TITAN) += fixups-titan.o

67
arch/sh/drivers/pci/fixups-sdk7786.c 100644
View File

@ -0,0 +1,67 @@
/*
* SDK7786 FPGA PCIe mux handling
*
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#define pr_fmt(fmt) "PCI: " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <mach/fpga.h>
/*
* The SDK7786 FPGA supports mangling of most of the slots in some way or
* another. Slots 3/4 are special in that only one can be supported at a
* time, and both appear on port 3 to the PCI bus scan. Enabling slot 4
* (the horizontal edge connector) will disable slot 3 entirely.
*
* Misconfigurations can be detected through the FPGA via the slot
* resistors to determine card presence. Hotplug remains unsupported.
*/
static unsigned int slot4en __devinitdata;
char *__devinit pcibios_setup(char *str)
{
if (strcmp(str, "slot4en") == 0) {
slot4en = 1;
return NULL;
}
return str;
}
static int __init sdk7786_pci_init(void)
{
u16 data = fpga_read_reg(PCIECR);
/*
* Enable slot #4 if it's been specified on the command line.
*
* Optionally reroute if slot #4 has a card present while slot #3
* does not, regardless of command line value.
*
* Card presence is logically inverted.
*/
slot4en ?: (!(data & PCIECR_PRST4) && (data & PCIECR_PRST3));
if (slot4en) {
pr_info("Activating PCIe slot#4 (disabling slot#3)\n");
data &= ~PCIECR_PCIEMUX1;
fpga_write_reg(data, PCIECR);
/* Warn about forced rerouting if slot#3 is occupied */
if ((data & PCIECR_PRST3) == 0) {
pr_warning("Unreachable card detected in slot#3\n");
return -EBUSY;
}
} else
pr_info("PCIe slot#4 disabled\n");
return 0;
}
postcore_initcall(sdk7786_pci_init);

11
arch/sh/drivers/pci/ops-sh4.c
View File

@ -9,6 +9,7 @@
*/
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <asm/addrspace.h>
#include "pci-sh4.h"
@ -18,8 +19,6 @@
#define CONFIG_CMD(bus, devfn, where) \
(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
static DEFINE_SPINLOCK(sh4_pci_lock);
/*
* Functions for accessing PCI configuration space with type 1 accesses
*/
@ -34,10 +33,10 @@ static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
* PCIPDR may only be accessed as 32 bit words,
* so we must do byte alignment by hand
*/
spin_lock_irqsave(&sh4_pci_lock, flags);
raw_spin_lock_irqsave(&pci_config_lock, flags);
pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
data = pci_read_reg(chan, SH4_PCIPDR);
spin_unlock_irqrestore(&sh4_pci_lock, flags);
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
switch (size) {
case 1:
@ -69,10 +68,10 @@ static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
int shift;
u32 data;
spin_lock_irqsave(&sh4_pci_lock, flags);
raw_spin_lock_irqsave(&pci_config_lock, flags);
pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
data = pci_read_reg(chan, SH4_PCIPDR);
spin_unlock_irqrestore(&sh4_pci_lock, flags);
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
switch (size) {
case 1:

69
arch/sh/drivers/pci/ops-sh7786.c
View File

@ -1,7 +1,7 @@
/*
* Generic SH7786 PCI-Express operations.
*
* Copyright (C) 2009 Paul Mundt
* Copyright (C) 2009 - 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License v2. See the file "COPYING" in the main directory of this archive
@ -19,37 +19,72 @@ enum {
PCI_ACCESS_WRITE,
};
static DEFINE_SPINLOCK(sh7786_pcie_lock);
static int sh7786_pcie_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
{
struct pci_channel *chan = bus->sysdata;
int dev, func;
int dev, func, type, reg;
dev = PCI_SLOT(devfn);
func = PCI_FUNC(devfn);
type = !!bus->parent;
reg = where & ~3;
if (bus->number > 255 || dev > 31 || func > 7)
return PCIBIOS_FUNC_NOT_SUPPORTED;
if (devfn)
return PCIBIOS_DEVICE_NOT_FOUND;
/*
* While each channel has its own memory-mapped extended config
* space, it's generally only accessible when in endpoint mode.
* When in root complex mode, the controller is unable to target
* itself with either type 0 or type 1 accesses, and indeed, any
* controller initiated target transfer to its own config space
* result in a completer abort.
*
* Each channel effectively only supports a single device, but as
* the same channel <-> device access works for any PCI_SLOT()
* value, we cheat a bit here and bind the controller's config
* space to devfn 0 in order to enable self-enumeration. In this
* case the regular PAR/PDR path is sidelined and the mangled
* config access itself is initiated as a SuperHyway transaction.
*/
if (pci_is_root_bus(bus)) {
if (dev == 0) {
if (access_type == PCI_ACCESS_READ)
*data = pci_read_reg(chan, PCI_REG(reg));
else
pci_write_reg(chan, *data, PCI_REG(reg));
return PCIBIOS_SUCCESSFUL;
} else if (dev > 1)
return PCIBIOS_DEVICE_NOT_FOUND;
}
/* Clear errors */
pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR);
/* Set the PIO address */
pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
(func << 16) | (where & ~3), SH4A_PCIEPAR);
(func << 16) | reg, SH4A_PCIEPAR);
/* Enable the configuration access */
pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR);
pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR);
/* Check for errors */
if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10)
return PCIBIOS_DEVICE_NOT_FOUND;
/* Check for master and target aborts */
if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
return PCIBIOS_DEVICE_NOT_FOUND;
if (access_type == PCI_ACCESS_READ)
*data = pci_read_reg(chan, SH4A_PCIEPDR);
else
pci_write_reg(chan, *data, SH4A_PCIEPDR);
/* Check for master and target aborts */
if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
return PCIBIOS_DEVICE_NOT_FOUND;
/* Disable the configuration access */
pci_write_reg(chan, 0, SH4A_PCIEPCTLR);
return PCIBIOS_SUCCESSFUL;
}
@ -66,11 +101,13 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
else if ((size == 4) && (where & 3))
return PCIBIOS_BAD_REGISTER_NUMBER;
spin_lock_irqsave(&sh7786_pcie_lock, flags);
raw_spin_lock_irqsave(&pci_config_lock, flags);
ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
devfn, where, &data);
if (ret != PCIBIOS_SUCCESSFUL)
if (ret != PCIBIOS_SUCCESSFUL) {
*val = 0xffffffff;
goto out;
}
if (size == 1)
*val = (data >> ((where & 3) << 3)) & 0xff;
@ -84,7 +121,7 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
devfn, where, size, (unsigned long)*val);
out:
spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
return ret;
}
@ -100,7 +137,7 @@ static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
else if ((size == 4) && (where & 3))
return PCIBIOS_BAD_REGISTER_NUMBER;
spin_lock_irqsave(&sh7786_pcie_lock, flags);
raw_spin_lock_irqsave(&pci_config_lock, flags);
ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
devfn, where, &data);
if (ret != PCIBIOS_SUCCESSFUL)
@ -124,7 +161,7 @@ static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus,
devfn, where, &data);
out:
spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
return ret;
}

2
arch/sh/drivers/pci/pci-sh7751.c
View File

@ -81,7 +81,7 @@ static int __init sh7751_pci_init(void)
unsigned int id;
u32 word, reg;
printk(KERN_NOTICE "PCI: Starting intialization.\n");
printk(KERN_NOTICE "PCI: Starting initialization.\n");
chan->reg_base = 0xfe200000;

2
arch/sh/drivers/pci/pci-sh7780.c
View File

@ -246,7 +246,7 @@ static int __init sh7780_pci_init(void)
const char *type;
int ret, i;
printk(KERN_NOTICE "PCI: Starting intialization.\n");
printk(KERN_NOTICE "PCI: Starting initialization.\n");
chan->reg_base = 0xfe040000;

6
arch/sh/drivers/pci/pci-sh7780.h
View File

@ -12,12 +12,6 @@
#ifndef _PCI_SH7780_H_
#define _PCI_SH7780_H_
#define PCI_VENDOR_ID_RENESAS 0x1912
#define PCI_DEVICE_ID_RENESAS_SH7781 0x0001
#define PCI_DEVICE_ID_RENESAS_SH7780 0x0002
#define PCI_DEVICE_ID_RENESAS_SH7763 0x0004
#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007
/* SH7780 Control Registers */
#define PCIECR 0xFE000008
#define PCIECR_ENBL 0x01

43
arch/sh/drivers/pci/pci.c
View File

@ -19,6 +19,7 @@
#include <linux/dma-debug.h>
#include <linux/io.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>
unsigned long PCIBIOS_MIN_IO = 0x0000;
unsigned long PCIBIOS_MIN_MEM = 0;
@ -56,6 +57,11 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
}
}
/*
* This interrupt-safe spinlock protects all accesses to PCI
* configuration space.
*/
DEFINE_RAW_SPINLOCK(pci_config_lock);
static DEFINE_MUTEX(pci_scan_mutex);
int __devinit register_pci_controller(struct pci_channel *hose)
@ -233,40 +239,7 @@ void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
u16 cmd, old_cmd;
int idx;
struct resource *r;
pci_read_config_word(dev, PCI_COMMAND, &cmd);
old_cmd = cmd;
for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
/* Only set up the requested stuff */
if (!(mask & (1<<idx)))
continue;
r = &dev->resource[idx];
if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
continue;
if ((idx == PCI_ROM_RESOURCE) &&
(!(r->flags & IORESOURCE_ROM_ENABLE)))
continue;
if (!r->start && r->end) {
printk(KERN_ERR "PCI: Device %s not available "
"because of resource collisions\n",
pci_name(dev));
return -EINVAL;
}
if (r->flags & IORESOURCE_IO)
cmd |= PCI_COMMAND_IO;
if (r->flags & IORESOURCE_MEM)
cmd |= PCI_COMMAND_MEMORY;
}
if (cmd != old_cmd) {
printk("PCI: Enabling device %s (%04x -> %04x)\n",
pci_name(dev), old_cmd, cmd);
pci_write_config_word(dev, PCI_COMMAND, cmd);
}
return 0;
return pci_enable_resources(dev, mask);
}
/*
@ -295,7 +268,7 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq)
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}
char * __devinit pcibios_setup(char *str)
char * __devinit __weak pcibios_setup(char *str)
{
return str;
}

253
arch/sh/drivers/pci/pcie-sh7786.c
View File

@ -13,11 +13,14 @@
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/sh_clk.h>
#include "pcie-sh7786.h"
#include <asm/sizes.h>
struct sh7786_pcie_port {
struct pci_channel *hose;
struct clk *fclk, phy_clk;
unsigned int index;
int endpoint;
int link;
@ -51,6 +54,7 @@ static struct resource sh7786_pci0_resources[] = {
.name = "PCIe0 MEM 2",
.start = 0xfe100000,
.end = 0xfe100000 + SZ_1M - 1,
.flags = IORESOURCE_MEM,
},
};
@ -74,6 +78,7 @@ static struct resource sh7786_pci1_resources[] = {
.name = "PCIe1 MEM 2",
.start = 0xfe300000,
.end = 0xfe300000 + SZ_1M - 1,
.flags = IORESOURCE_MEM,
},
};
@ -82,6 +87,7 @@ static struct resource sh7786_pci2_resources[] = {
.name = "PCIe2 IO",
.start = 0xfc800000,
.end = 0xfc800000 + SZ_4M - 1,
.flags = IORESOURCE_IO,
}, {
.name = "PCIe2 MEM 0",
.start = 0x80000000,
@ -96,6 +102,7 @@ static struct resource sh7786_pci2_resources[] = {
.name = "PCIe2 MEM 2",
.start = 0xfcd00000,
.end = 0xfcd00000 + SZ_1M - 1,
.flags = IORESOURCE_MEM,
},
};
@ -117,7 +124,29 @@ static struct pci_channel sh7786_pci_channels[] = {
DEFINE_CONTROLLER(0xfcc00000, 2),
};
static int phy_wait_for_ack(struct pci_channel *chan)
static struct clk fixed_pciexclkp = {
.rate = 100000000, /* 100 MHz reference clock */
};
static void __devinit sh7786_pci_fixup(struct pci_dev *dev)
{
/*
* Prevent enumeration of root complex resources.
*/
if (pci_is_root_bus(dev->bus) && dev->devfn == 0) {
int i;
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
dev->resource[i].flags = 0;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_SH7786,
sh7786_pci_fixup);
static int __init phy_wait_for_ack(struct pci_channel *chan)
{
unsigned int timeout = 100;
@ -131,7 +160,7 @@ static int phy_wait_for_ack(struct pci_channel *chan)
return -ETIMEDOUT;
}
static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
{
unsigned int timeout = 100;
@ -145,19 +174,14 @@ static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
return -ETIMEDOUT;
}
static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
unsigned int lane, unsigned int data)
static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr,
unsigned int lane, unsigned int data)
{
unsigned long phyaddr, ctrl;
unsigned long phyaddr;
phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
((addr & 0xff) << BITS_ADR);
/* Enable clock */
ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
ctrl |= (1 << BITS_CKE);
pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
/* Set write data */
pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
@ -165,20 +189,74 @@ static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
phy_wait_for_ack(chan);
/* Clear command */
pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
phy_wait_for_ack(chan);
/* Disable clock */
ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
ctrl &= ~(1 << BITS_CKE);
pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
}
static int phy_init(struct pci_channel *chan)
static int __init pcie_clk_init(struct sh7786_pcie_port *port)
{
struct pci_channel *chan = port->hose;
struct clk *clk;
char fclk_name[16];
int ret;
/*
* First register the fixed clock
*/
ret = clk_register(&fixed_pciexclkp);
if (unlikely(ret != 0))
return ret;
/*
* Grab the port's function clock, which the PHY clock depends
* on. clock lookups don't help us much at this point, since no
* dev_id is available this early. Lame.
*/
snprintf(fclk_name, sizeof(fclk_name), "pcie%d_fck", port->index);
port->fclk = clk_get(NULL, fclk_name);
if (IS_ERR(port->fclk)) {
ret = PTR_ERR(port->fclk);
goto err_fclk;
}
clk_enable(port->fclk);
/*
* And now, set up the PHY clock
*/
clk = &port->phy_clk;
memset(clk, 0, sizeof(struct clk));
clk->parent = &fixed_pciexclkp;
clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR);
clk->enable_bit = BITS_CKE;
ret = sh_clk_mstp32_register(clk, 1);
if (unlikely(ret < 0))
goto err_phy;
return 0;
err_phy:
clk_disable(port->fclk);
clk_put(port->fclk);
err_fclk:
clk_unregister(&fixed_pciexclkp);
return ret;
}
static int __init phy_init(struct sh7786_pcie_port *port)
{
struct pci_channel *chan = port->hose;
unsigned int timeout = 100;
clk_enable(&port->phy_clk);
/* Initialize the phy */
phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
@ -187,9 +265,13 @@ static int phy_init(struct pci_channel *chan)
phy_write_reg(chan, 0x66, 0xf, 0x00000010);
phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
/* Deassert Standby */
phy_write_reg(chan, 0x67, 0xf, 0x00000400);
phy_write_reg(chan, 0x67, 0x1, 0x00000400);
/* Disable clock */
clk_disable(&port->phy_clk);
while (timeout--) {
if (pci_read_reg(chan, SH4A_PCIEPHYSR))
@ -201,22 +283,33 @@ static int phy_init(struct pci_channel *chan)
return -ETIMEDOUT;
}
static int pcie_init(struct sh7786_pcie_port *port)
static void __init pcie_reset(struct sh7786_pcie_port *port)
{
struct pci_channel *chan = port->hose;
pci_write_reg(chan, 1, SH4A_PCIESRSTR);
pci_write_reg(chan, 0, SH4A_PCIETCTLR);
pci_write_reg(chan, 0, SH4A_PCIESRSTR);
pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
}
static int __init pcie_init(struct sh7786_pcie_port *port)
{
struct pci_channel *chan = port->hose;
unsigned int data;
phys_addr_t memphys;
size_t memsize;
int ret, i;
int ret, i, win;
/* Begin initialization */
pci_write_reg(chan, 0, SH4A_PCIETCTLR);
pcie_reset(port);
/* Initialize as type1. */
data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
data &= ~(0x7f << 16);
data |= PCI_HEADER_TYPE_BRIDGE << 16;
pci_write_reg(chan, data, SH4A_PCIEPCICONF3);
/*
* Initial header for port config space is type 1, set the device
* class to match. Hardware takes care of propagating the IDSETR
* settings, so there is no need to bother with a quirk.
*/
pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI << 16, SH4A_PCIEIDSETR1);
/* Initialize default capabilities. */
data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
@ -268,30 +361,33 @@ static int pcie_init(struct sh7786_pcie_port *port)
* LAR1/LAMR1.
*/
if (memsize > SZ_512M) {
__raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
__raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
chan->reg_base + SH4A_PCIELAMR1);
pci_write_reg(chan, memphys + SZ_512M, SH4A_PCIELAR1);
pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,
SH4A_PCIELAMR1);
memsize = SZ_512M;
} else {
/*
* Otherwise just zero it out and disable it.
*/
__raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
__raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
pci_write_reg(chan, 0, SH4A_PCIELAR1);
pci_write_reg(chan, 0, SH4A_PCIELAMR1);
}
/*
* LAR0/LAMR0 covers up to the first 512MB, which is enough to
* cover all of lowmem on most platforms.
*/
__raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
__raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
pci_write_reg(chan, memphys, SH4A_PCIELAR0);
pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);
/* Finish initialization */
data = pci_read_reg(chan, SH4A_PCIETCTLR);
data |= 0x1;
pci_write_reg(chan, data, SH4A_PCIETCTLR);
/* Let things settle down a bit.. */
mdelay(100);
/* Enable DL_Active Interrupt generation */
data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
data |= PCIEDLINTENR_DLL_ACT_ENABLE;
@ -302,9 +398,12 @@ static int pcie_init(struct sh7786_pcie_port *port)
data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);
pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
/*
* This will timeout if we don't have a link, but we permit the
* port to register anyways in order to support hotplug on future
* hardware.
*/
ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
if (unlikely(ret != 0))
return -ENODEV;
data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
@ -317,35 +416,48 @@ static int pcie_init(struct sh7786_pcie_port *port)
wmb();
data = pci_read_reg(chan, SH4A_PCIEMACSR);
printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
port->index, (data >> 20) & 0x3f);
if (ret == 0) {
data = pci_read_reg(chan, SH4A_PCIEMACSR);
printk(KERN_NOTICE "PCI: PCIe#%d x%d link detected\n",
port->index, (data >> 20) & 0x3f);
} else
printk(KERN_NOTICE "PCI: PCIe#%d link down\n",
port->index);
for (i = 0; i < chan->nr_resources; i++) {
for (i = win = 0; i < chan->nr_resources; i++) {
struct resource *res = chan->resources + i;
resource_size_t size;
u32 enable_mask;
u32 mask;
pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
/*
* We can't use the 32-bit mode windows in legacy 29-bit
* mode, so just skip them entirely.
*/
if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
continue;
size = resource_size(res);
pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
/*
* The PAMR mask is calculated in units of 256kB, which
* keeps things pretty simple.
*/
__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
chan->reg_base + SH4A_PCIEPAMR(i));
size = resource_size(res);
mask = (roundup_pow_of_two(size) / SZ_256K) - 1;
pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win));
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i));
pci_write_reg(chan, upper_32_bits(res->start),
SH4A_PCIEPARH(win));
pci_write_reg(chan, lower_32_bits(res->start),
SH4A_PCIEPARL(win));
enable_mask = MASK_PARE;
mask = MASK_PARE;
if (res->flags & IORESOURCE_IO)
enable_mask |= MASK_SPC;
mask |= MASK_SPC;
pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win));
win++;
}
return 0;
@ -356,26 +468,33 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
return 71;
}
static int sh7786_pcie_core_init(void)
static int __init sh7786_pcie_core_init(void)
{
/* Return the number of ports */
return test_mode_pin(MODE_PIN12) ? 3 : 2;
}
static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
static int __init sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
{
int ret;
ret = phy_init(port->hose);
if (unlikely(ret < 0))
return ret;
/*
* Check if we are configured in endpoint or root complex mode,
* this is a fixed pin setting that applies to all PCIe ports.
*/
port->endpoint = test_mode_pin(MODE_PIN11);
/*
* Setup clocks, needed both for PHY and PCIe registers.
*/
ret = pcie_clk_init(port);
if (unlikely(ret < 0))
return ret;
ret = phy_init(port);
if (unlikely(ret < 0))
return ret;
ret = pcie_init(port);
if (unlikely(ret < 0))
return ret;
@ -390,9 +509,10 @@ static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
static int __init sh7786_pcie_init(void)
{
struct clk *platclk;
int ret = 0, i;
printk(KERN_NOTICE "PCI: Starting intialization.\n");
printk(KERN_NOTICE "PCI: Starting initialization.\n");
sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;
@ -407,6 +527,22 @@ static int __init sh7786_pcie_init(void)
if (unlikely(!sh7786_pcie_ports))
return -ENOMEM;
/*
* Fetch any optional platform clock associated with this block.
*
* This is a rather nasty hack for boards with spec-mocking FPGAs
* that have a secondary set of clocks outside of the on-chip
* ones that need to be accounted for before there is any chance
* of touching the existing MSTP bits or CPG clocks.
*/
platclk = clk_get(NULL, "pcie_plat_clk");
if (IS_ERR(platclk)) {
/* Sane hardware should probably get a WARN_ON.. */
platclk = NULL;
}
clk_enable(platclk);
printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
for (i = 0; i < nr_ports; i++) {
@ -419,8 +555,11 @@ static int __init sh7786_pcie_init(void)
ret |= sh7786_pcie_hwops->port_init_hw(port);
}
if (unlikely(ret))
if (unlikely(ret)) {
clk_disable(platclk);
clk_put(platclk);
return ret;
}
return 0;
}

56
arch/sh/drivers/pci/pcie-sh7786.h
View File

@ -55,8 +55,11 @@
#define BITS_ERRRCV (0) /* 0 ERRRCV 0 */
#define MASK_ERRRCV (1<<BITS_ERRRCV)
/* PCIEENBLR */
#define SH4A_PCIEENBLR (0x000008) /* R/W - 0x0000 0001 32 */
/* PCIEECR */
#define SH4A_PCIEECR (0x000008) /* R/W - 0x0000 0000 32 */
#define SH4A_PCIEECR (0x00000C) /* R/W - 0x0000 0000 32 */
#define BITS_ENBL (0) /* 0 ENBL 0 R/W */
#define MASK_ENBL (1<<BITS_ENBL)
@ -113,6 +116,27 @@
#define BITS_MDATA (0)
#define MASK_MDATA (0xffffffff<<BITS_MDATA)
/* PCIEUNLOCKCR */
#define SH4A_PCIEUNLOCKCR (0x000048) /* R/W - 0x0000 0000 32 */
/* PCIEIDR */
#define SH4A_PCIEIDR (0x000060) /* R/W - 0x0101 1101 32 */
/* PCIEDBGCTLR */
#define SH4A_PCIEDBGCTLR (0x000100) /* R/W - 0x0000 0000 32 */
/* PCIEINTXR */
#define SH4A_PCIEINTXR (0x004000) /* R/W - 0x0000 0000 32 */
/* PCIERMSGR */
#define SH4A_PCIERMSGR (0x004010) /* R/W - 0x0000 0000 32 */
/* PCIERSTR */
#define SH4A_PCIERSTR(x) (0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */
/* PCIESRSTR */
#define SH4A_PCIESRSTR (0x008040) /* R/W - 0x0000 0000 32 */
/* PCIEPHYCTLR */
#define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */
#define BITS_CKE (0)
@ -121,6 +145,9 @@
/* PCIERMSGIER */
#define SH4A_PCIERMSGIER (0x004040) /* R/W - 0x0000 0000 32 */
/* PCIEPHYCTLR */
#define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */
/* PCIEPHYADRR */
#define SH4A_PCIEPHYADRR (0x010004) /* R/W - 0x0000 0000 32 */
#define BITS_ACK (24) // Rev1.171
@ -152,7 +179,7 @@
#define MASK_CFINT (1<<BITS_CFINT)
/* PCIETSTR */
#define SH4A_PCIETSTR (0x020004) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIETSTR (0x020004) /* R 0x0000 0000 32 */
/* PCIEINTR */
#define SH4A_PCIEINTR (0x020008) /* R/W R/W 0x0000 0000 32 */
@ -236,6 +263,9 @@
#define BITS_INTPM (8)
#define MASK_INTPM (1<<BITS_INTPM)
/* PCIEEH0R */
#define SH4A_PCIEEHR(x) (0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */
/* PCIEAIR */
#define SH4A_PCIEAIR (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */
@ -244,6 +274,25 @@
/* PCIEERRFR */ // Rev1.18
#define SH4A_PCIEERRFR (0x020020) /* R/W R/W 0xxxxx xxxx 32 */ // Rev1.18
/* PCIEERRFER */
#define SH4A_PCIEERRFER (0x020024) /* R/W R/W 0x0000 0000 32 */
/* PCIEERRFR2 */
#define SH4A_PCIEERRFR2 (0x020028) /* R/W R/W 0x0000 0000 32 */
/* PCIEMSIR */
#define SH4A_PCIEMSIR (0x020040) /* R/W - 0x0000 0000 32 */
/* PCIEMSIFR */
#define SH4A_PCIEMSIFR (0x020044) /* R/W R/W 0x0000 0000 32 */
/* PCIEPWRCTLR */
#define SH4A_PCIEPWRCTLR (0x020100) /* R/W - 0x0000 0000 32 */
/* PCIEPCCTLR */
#define SH4A_PCIEPCCTLR (0x020180) /* R/W - 0x0000 0000 32 */
// Rev1.18
/* PCIELAR0 */
#define SH4A_PCIELAR0 (0x020200) /* R/W R/W 0x0000 0000 32 */
@ -352,6 +401,7 @@
#define SH4A_PCIEDMCCR0 (0x021120) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMCC2R0 (0x021124) /* R/W R/W 0x0000 0000 - */
#define SH4A_PCIEDMCCCR0 (0x021128) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMCHSR0 (0x02112C) /* R/W - 0x0000 0000 32 */
#define SH4A_PCIEDMSAR1 (0x021140) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMSAHR1 (0x021144) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMDAR1 (0x021148) /* R/W R/W 0x0000 0000 32 */
@ -363,6 +413,7 @@
#define SH4A_PCIEDMCCR1 (0x021160) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMCC2R1 (0x021164) /* R/W R/W 0x0000 0000 - */
#define SH4A_PCIEDMCCCR1 (0x021168) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMCHSR1 (0x02116C) /* R/W - 0x0000 0000 32 */
#define SH4A_PCIEDMSAR2 (0x021180) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMSAHR2 (0x021184) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMDAR2 (0x021188) /* R/W R/W 0x0000 0000 32 */
@ -385,6 +436,7 @@
#define SH4A_PCIEDMCCR3 (0x0211E0) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMCC2R3 (0x0211E4) /* R/W R/W 0x0000 0000 - */
#define SH4A_PCIEDMCCCR3 (0x0211E8) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMCHSR3 (0x0211EC) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEPCICONF0 (0x040000) /* R R - 8/16/32 */
#define SH4A_PCIEPCICONF1 (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */
#define SH4A_PCIEPCICONF2 (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */

2
arch/sh/include/asm/Kbuild
View File

@ -5,5 +5,7 @@ header-y += cpu-features.h
header-y += hw_breakpoint.h
header-y += posix_types_32.h
header-y += posix_types_64.h
header-y += ptrace_32.h
header-y += ptrace_64.h
header-y += unistd_32.h
header-y += unistd_64.h

27
arch/sh/include/asm/elf.h
View File

@ -50,25 +50,14 @@
#define R_SH_GOTPC 167
/* FDPIC relocs */
#define R_SH_GOT20 70
#define R_SH_GOTOFF20 71
#define R_SH_GOTFUNCDESC 72
#define R_SH_GOTFUNCDESC20 73
#define R_SH_GOTOFFFUNCDESC 74
#define R_SH_GOTOFFFUNCDESC20 75
#define R_SH_FUNCDESC 76
#define R_SH_FUNCDESC_VALUE 77
#if 0 /* XXX - later .. */
#define R_SH_GOT20 198
#define R_SH_GOTOFF20 199
#define R_SH_GOTFUNCDESC 200
#define R_SH_GOTFUNCDESC20 201
#define R_SH_GOTOFFFUNCDESC 202
#define R_SH_GOTOFFFUNCDESC20 203
#define R_SH_FUNCDESC 204
#define R_SH_FUNCDESC_VALUE 205
#endif
#define R_SH_GOT20 201
#define R_SH_GOTOFF20 202
#define R_SH_GOTFUNCDESC 203
#define R_SH_GOTFUNCDESC20 204
#define R_SH_GOTOFFFUNCDESC 205
#define R_SH_GOTOFFFUNCDESC20 206
#define R_SH_FUNCDESC 207
#define R_SH_FUNCDESC_VALUE 208
/* SHmedia relocs */
#define R_SH_IMM_LOW16 246

4
arch/sh/include/asm/fixmap.h
View File

@ -58,7 +58,7 @@ enum fixed_addresses {
#ifdef CONFIG_HIGHMEM
FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS) - 1,
#endif
#ifdef CONFIG_IOREMAP_FIXED
@ -69,7 +69,7 @@ enum fixed_addresses {
*/
#define FIX_N_IOREMAPS 32
FIX_IOREMAP_BEGIN,
FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS,
FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS - 1,
#endif
__end_of_fixed_addresses

6
arch/sh/include/asm/gpio.h
View File

@ -41,14 +41,12 @@ static inline int gpio_cansleep(unsigned gpio)
static inline int gpio_to_irq(unsigned gpio)
{
WARN_ON(1);
return -ENOSYS;
return __gpio_to_irq(gpio);
}
static inline int irq_to_gpio(unsigned int irq)
{
WARN_ON(1);
return -EINVAL;
return -ENOSYS;
}
#endif /* CONFIG_GPIOLIB */

2
arch/sh/include/asm/irq.h
View File

@ -9,7 +9,7 @@
* advised to cap this at the hard limit that they're interested in
* through the machvec.
*/
#define NR_IRQS 256
#define NR_IRQS 512
#define NR_IRQS_LEGACY 8 /* Legacy external IRQ0-7 */
/*

1
arch/sh/include/asm/kprobes.h
View File

@ -16,7 +16,6 @@ typedef insn_size_t kprobe_opcode_t;
? (MAX_STACK_SIZE) \
: (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
#define regs_return_value(_regs) ((_regs)->regs[0])
#define flush_insn_slot(p) do { } while (0)
#define kretprobe_blacklist_size 0

2
arch/sh/include/asm/pci.h
View File

@ -37,6 +37,8 @@ struct pci_channel {
};
/* arch/sh/drivers/pci/pci.c */
extern raw_spinlock_t pci_config_lock;
extern int register_pci_controller(struct pci_channel *hose);
extern void pcibios_report_status(unsigned int status_mask, int warn);

3
arch/sh/include/asm/processor_32.h
View File

@ -13,7 +13,6 @@
#include <linux/linkage.h>
#include <asm/page.h>
#include <asm/types.h>
#include <asm/ptrace.h>
#include <asm/hw_breakpoint.h>
/*
@ -194,8 +193,6 @@ extern unsigned long get_wchan(struct task_struct *p);
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15])
#define user_stack_pointer(_regs) ((_regs)->regs[15])
#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
#define PREFETCH_STRIDE L1_CACHE_BYTES
#define ARCH_HAS_PREFETCH

3
arch/sh/include/asm/processor_64.h
View File

@ -17,7 +17,6 @@
#include <linux/compiler.h>
#include <asm/page.h>
#include <asm/types.h>
#include <asm/ptrace.h>
#include <cpu/registers.h>
/*
@ -231,7 +230,5 @@ extern unsigned long get_wchan(struct task_struct *p);
#define KSTK_EIP(tsk) ((tsk)->thread.pc)
#define KSTK_ESP(tsk) ((tsk)->thread.sp)
#define user_stack_pointer(_regs) ((_regs)->regs[15])
#endif /* __ASSEMBLY__ */
#endif /* __ASM_SH_PROCESSOR_64_H */

173
arch/sh/include/asm/ptrace.h
View File

@ -3,90 +3,7 @@
/*
* Copyright (C) 1999, 2000 Niibe Yutaka
*
*/
#if defined(__SH5__)
struct pt_regs {
unsigned long long pc;
unsigned long long sr;
long long syscall_nr;
unsigned long long regs[63];
unsigned long long tregs[8];
unsigned long long pad[2];
};
#else
/*
* GCC defines register number like this:
* -----------------------------
* 0 - 15 are integer registers
* 17 - 22 are control/special registers
* 24 - 39 fp registers
* 40 - 47 xd registers
* 48 - fpscr register
* -----------------------------
*
* We follows above, except:
* 16 --- program counter (PC)
* 22 --- syscall #
* 23 --- floating point communication register
*/
#define REG_REG0 0
#define REG_REG15 15
#define REG_PC 16
#define REG_PR 17
#define REG_SR 18
#define REG_GBR 19
#define REG_MACH 20
#define REG_MACL 21
#define REG_SYSCALL 22
#define REG_FPREG0 23
#define REG_FPREG15 38
#define REG_XFREG0 39
#define REG_XFREG15 54
#define REG_FPSCR 55
#define REG_FPUL 56
/*
* This struct defines the way the registers are stored on the
* kernel stack during a system call or other kernel entry.
*/
struct pt_regs {
unsigned long regs[16];
unsigned long pc;
unsigned long pr;
unsigned long sr;
unsigned long gbr;
unsigned long mach;
unsigned long macl;
long tra;
};
/*
* This struct defines the way the DSP registers are stored on the
* kernel stack during a system call or other kernel entry.
*/
struct pt_dspregs {
unsigned long a1;
unsigned long a0g;
unsigned long a1g;
unsigned long m0;
unsigned long m1;
unsigned long a0;
unsigned long x0;
unsigned long x1;
unsigned long y0;
unsigned long y1;
unsigned long dsr;
unsigned long rs;
unsigned long re;
unsigned long mod;
};
#endif
#define PTRACE_GETREGS 12 /* General registers */
#define PTRACE_SETREGS 13
@ -107,23 +24,103 @@ struct pt_dspregs {
#define PT_DATA_ADDR 248 /* &(struct user)->start_data */
#define PT_TEXT_LEN 252
#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
#include "ptrace_64.h"
#else
#include "ptrace_32.h"
#endif
#ifdef __KERNEL__
#include <linux/stringify.h>
#include <linux/stddef.h>
#include <linux/thread_info.h>
#include <asm/addrspace.h>
#include <asm/page.h>
#include <asm/system.h>
#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
#define user_stack_pointer(regs) ((unsigned long)(regs)->regs[15])
#define kernel_stack_pointer(regs) ((unsigned long)(regs)->regs[15])
#define instruction_pointer(regs) ((unsigned long)(regs)->pc)
extern void show_regs(struct pt_regs *);
/*
* These are defined as per linux/ptrace.h.
*/
struct task_struct;
#define arch_has_single_step() (1)
/*
* kprobe-based event tracer support
*/
struct pt_regs_offset {
const char *name;
int offset;
};
#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
#define REGS_OFFSET_NAME(num) \
{.name = __stringify(r##num), .offset = offsetof(struct pt_regs, regs[num])}
#define TREGS_OFFSET_NAME(num) \
{.name = __stringify(tr##num), .offset = offsetof(struct pt_regs, tregs[num])}
#define REG_OFFSET_END {.name = NULL, .offset = 0}
/* Query offset/name of register from its name/offset */
extern int regs_query_register_offset(const char *name);
extern const char *regs_query_register_name(unsigned int offset);
extern const struct pt_regs_offset regoffset_table[];
/**
* regs_get_register() - get register value from its offset
* @regs: pt_regs from which register value is gotten.
* @offset: offset number of the register.
*
* regs_get_register returns the value of a register. The @offset is the
* offset of the register in struct pt_regs address which specified by @regs.
* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
*/
static inline unsigned long regs_get_register(struct pt_regs *regs,
unsigned int offset)
{
if (unlikely(offset > MAX_REG_OFFSET))
return 0;
return *(unsigned long *)((unsigned long)regs + offset);
}
/**
* regs_within_kernel_stack() - check the address in the stack
* @regs: pt_regs which contains kernel stack pointer.
* @addr: address which is checked.
*
* regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
* If @addr is within the kernel stack, it returns true. If not, returns false.
*/
static inline int regs_within_kernel_stack(struct pt_regs *regs,
unsigned long addr)
{
return ((addr & ~(THREAD_SIZE - 1)) ==
(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
}
/**
* regs_get_kernel_stack_nth() - get Nth entry of the stack
* @regs: pt_regs which contains kernel stack pointer.
* @n: stack entry number.
*
* regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
* is specified by @regs. If the @n th entry is NOT in the kernel stack,
* this returns 0.
*/
static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
unsigned int n)
{
unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
addr += n;
if (regs_within_kernel_stack(regs, (unsigned long)addr))
return *addr;
else
return 0;
}
struct perf_event;
struct perf_sample_data;

83
arch/sh/include/asm/ptrace_32.h 100644
View File

@ -0,0 +1,83 @@
#ifndef __ASM_SH_PTRACE_32_H
#define __ASM_SH_PTRACE_32_H
/*
* GCC defines register number like this:
* -----------------------------
* 0 - 15 are integer registers
* 17 - 22 are control/special registers
* 24 - 39 fp registers
* 40 - 47 xd registers
* 48 - fpscr register
* -----------------------------
*
* We follows above, except:
* 16 --- program counter (PC)
* 22 --- syscall #
* 23 --- floating point communication register
*/
#define REG_REG0 0
#define REG_REG15 15
#define REG_PC 16
#define REG_PR 17
#define REG_SR 18
#define REG_GBR 19
#define REG_MACH 20
#define REG_MACL 21
#define REG_SYSCALL 22
#define REG_FPREG0 23
#define REG_FPREG15 38
#define REG_XFREG0 39
#define REG_XFREG15 54
#define REG_FPSCR 55
#define REG_FPUL 56
/*
* This struct defines the way the registers are stored on the
* kernel stack during a system call or other kernel entry.
*/
struct pt_regs {
unsigned long regs[16];
unsigned long pc;
unsigned long pr;
unsigned long sr;
unsigned long gbr;
unsigned long mach;
unsigned long macl;
long tra;
};
/*
* This struct defines the way the DSP registers are stored on the
* kernel stack during a system call or other kernel entry.
*/
struct pt_dspregs {
unsigned long a1;
unsigned long a0g;
unsigned long a1g;
unsigned long m0;
unsigned long m1;
unsigned long a0;
unsigned long x0;
unsigned long x1;
unsigned long y0;
unsigned long y1;
unsigned long dsr;
unsigned long rs;
unsigned long re;
unsigned long mod;
};
#ifdef __KERNEL__
#define MAX_REG_OFFSET offsetof(struct pt_regs, tra)
#define regs_return_value(regs) ((regs)->regs[0])
#endif /* __KERNEL__ */
#endif /* __ASM_SH_PTRACE_32_H */

20
arch/sh/include/asm/ptrace_64.h 100644
View File

@ -0,0 +1,20 @@
#ifndef __ASM_SH_PTRACE_64_H
#define __ASM_SH_PTRACE_64_H
struct pt_regs {
unsigned long long pc;
unsigned long long sr;
long long syscall_nr;
unsigned long long regs[63];
unsigned long long tregs[8];
unsigned long long pad[2];
};
#ifdef __KERNEL__
#define MAX_REG_OFFSET offsetof(struct pt_regs, tregs[7])
#define regs_return_value(regs) ((regs)->regs[3])
#endif /* __KERNEL__ */
#endif /* __ASM_SH_PTRACE_64_H */

1
arch/sh/include/asm/sizes.h
View File

@ -32,6 +32,7 @@
#define SZ_512 0x00000200
#define SZ_1K 0x00000400
#define SZ_2K 0x00000800
#define SZ_4K 0x00001000
#define SZ_8K 0x00002000
#define SZ_16K 0x00004000

38
arch/sh/include/asm/sram.h 100644
View File

@ -0,0 +1,38 @@
#ifndef __ASM_SRAM_H
#define __ASM_SRAM_H
#ifdef CONFIG_HAVE_SRAM_POOL
#include <linux/spinlock.h>
#include <linux/genalloc.h>
/* arch/sh/mm/sram.c */
extern struct gen_pool *sram_pool;
static inline unsigned long sram_alloc(size_t len)
{
if (!sram_pool)
return 0UL;
return gen_pool_alloc(sram_pool, len);
}
static inline void sram_free(unsigned long addr, size_t len)
{
return gen_pool_free(sram_pool, addr, len);
}
#else
static inline unsigned long sram_alloc(size_t len)
{
return 0;
}
static inline void sram_free(unsigned long addr, size_t len)
{
}
#endif /* CONFIG_HAVE_SRAM_POOL */
#endif /* __ASM_SRAM_H */

2
arch/sh/include/asm/system.h
View File

@ -140,8 +140,6 @@ extern unsigned int instruction_size(unsigned int insn);
extern unsigned long cached_to_uncached;
extern unsigned long uncached_size;
extern struct dentry *sh_debugfs_root;
void per_cpu_trap_init(void);
void default_idle(void);
void cpu_idle_wait(void);

15
arch/sh/include/asm/system_32.h
View File

@ -212,17 +212,16 @@ static inline reg_size_t register_align(void *val)
}
int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
struct mem_access *ma, int);
struct mem_access *ma, int, unsigned long address);
static inline void trigger_address_error(void)
{
if (__in_29bit_mode())
__asm__ __volatile__ (
"ldc %0, sr\n\t"
"mov.l @%1, %0"
:
: "r" (0x10000000), "r" (0x80000001)
);
__asm__ __volatile__ (
"ldc %0, sr\n\t"
"mov.l @%1, %0"
:
: "r" (0x10000000), "r" (0x80000001)
);
}
asmlinkage void do_address_error(struct pt_regs *regs,

2
arch/sh/include/asm/tlbflush.h
View File

@ -21,6 +21,8 @@ extern void local_flush_tlb_kernel_range(unsigned long start,
unsigned long end);
extern void local_flush_tlb_one(unsigned long asid, unsigned long page);
extern void __flush_tlb_global(void);
#ifdef CONFIG_SMP
extern void flush_tlb_all(void);

27
arch/sh/include/asm/unistd_32.h
View File

@ -345,13 +345,34 @@
#define __NR_pwritev 334
#define __NR_rt_tgsigqueueinfo 335
#define __NR_perf_event_open 336
#define __NR_fanotify_init 337
#define __NR_fanotify_mark 338
#define __NR_prlimit64 339
#define NR_syscalls 337
/* Non-multiplexed socket family */
#define __NR_socket 340
#define __NR_bind 341
#define __NR_connect 342
#define __NR_listen 343
#define __NR_accept 344
#define __NR_getsockname 345
#define __NR_getpeername 346
#define __NR_socketpair 347
#define __NR_send 348
#define __NR_sendto 349
#define __NR_recv 350
#define __NR_recvfrom 351
#define __NR_shutdown 352
#define __NR_setsockopt 353
#define __NR_getsockopt 354
#define __NR_sendmsg 355
#define __NR_recvmsg 356
#define __NR_recvmmsg 357
#define NR_syscalls 358
#ifdef __KERNEL__
#define __IGNORE_recvmmsg
#define __ARCH_WANT_IPC_PARSE_VERSION
#define __ARCH_WANT_OLD_READDIR
#define __ARCH_WANT_OLD_STAT

5
arch/sh/include/asm/unistd_64.h
View File

@ -387,10 +387,13 @@
#define __NR_perf_event_open 364
#define __NR_recvmmsg 365
#define __NR_accept4 366
#define __NR_fanotify_init 367
#define __NR_fanotify_mark 368
#define __NR_prlimit64 369
#ifdef __KERNEL__
#define NR_syscalls 367
#define NR_syscalls 370
#define __ARCH_WANT_IPC_PARSE_VERSION
#define __ARCH_WANT_OLD_READDIR

1
arch/sh/include/cpu-sh3/cpu/mmu_context.h
View File

@ -16,6 +16,7 @@
#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
#define MMUCR_TI (1 << 2) /* TLB flush bit */
#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
#define MMU_PAGE_ASSOC_BIT 0x80

4
arch/sh/include/cpu-sh4/cpu/freq.h
View File

@ -56,7 +56,9 @@
#define FRQCR1 0xffc40004
#define FRQMR1 0xffc40014
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
#define FRQCR 0xffc00014
#define FRQCR0 0xffc00000
#define FRQCR1 0xffc00004
#define FRQMR1 0xffc00014
#else
#define FRQCR 0xffc00000
#define FRQCR_PSTBY 0x0200

287
arch/sh/include/cpu-sh4/cpu/sh7757.h
View File

@ -3,241 +3,252 @@
enum {
/* PTA */
GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
GPIO_PTA0, GPIO_PTA1, GPIO_PTA2, GPIO_PTA3,
GPIO_PTA4, GPIO_PTA5, GPIO_PTA6, GPIO_PTA7,
/* PTB */
GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
GPIO_PTB0, GPIO_PTB1, GPIO_PTB2, GPIO_PTB3,
GPIO_PTB4, GPIO_PTB5, GPIO_PTB6, GPIO_PTB7,
/* PTC */
GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
GPIO_PTC0, GPIO_PTC1, GPIO_PTC2, GPIO_PTC3,
GPIO_PTC4, GPIO_PTC5, GPIO_PTC6, GPIO_PTC7,
/* PTD */
GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
GPIO_PTD0, GPIO_PTD1, GPIO_PTD2, GPIO_PTD3,
GPIO_PTD4, GPIO_PTD5, GPIO_PTD6, GPIO_PTD7,
/* PTE */
GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
GPIO_PTE0, GPIO_PTE1, GPIO_PTE2, GPIO_PTE3,
GPIO_PTE4, GPIO_PTE5, GPIO_PTE6, GPIO_PTE7,
/* PTF */
GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
GPIO_PTF0, GPIO_PTF1, GPIO_PTF2, GPIO_PTF3,
GPIO_PTF4, GPIO_PTF5, GPIO_PTF6, GPIO_PTF7,
/* PTG */
GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4,
GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
GPIO_PTG0, GPIO_PTG1, GPIO_PTG2, GPIO_PTG3,
GPIO_PTG4, GPIO_PTG5, GPIO_PTG6, GPIO_PTG7,
/* PTH */
GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
GPIO_PTH0, GPIO_PTH1, GPIO_PTH2, GPIO_PTH3,
GPIO_PTH4, GPIO_PTH5, GPIO_PTH6, GPIO_PTH7,
/* PTI */
GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4,
GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0,
GPIO_PTI0, GPIO_PTI1, GPIO_PTI2, GPIO_PTI3,
GPIO_PTI4, GPIO_PTI5, GPIO_PTI6, GPIO_PTI7,
/* PTJ */
GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4,
GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
GPIO_PTJ0, GPIO_PTJ1, GPIO_PTJ2, GPIO_PTJ3,
GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6, GPIO_PTJ7_RESV,
/* PTK */
GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
GPIO_PTK0, GPIO_PTK1, GPIO_PTK2, GPIO_PTK3,
GPIO_PTK4, GPIO_PTK5, GPIO_PTK6, GPIO_PTK7,
/* PTL */
GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
GPIO_PTL0, GPIO_PTL1, GPIO_PTL2, GPIO_PTL3,
GPIO_PTL4, GPIO_PTL5, GPIO_PTL6, GPIO_PTL7_RESV,
/* PTM */
GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
GPIO_PTM0, GPIO_PTM1, GPIO_PTM2, GPIO_PTM3,
GPIO_PTM4, GPIO_PTM5, GPIO_PTM6, GPIO_PTM7,
/* PTN */
GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
GPIO_PTN0, GPIO_PTN1, GPIO_PTN2, GPIO_PTN3,
GPIO_PTN4, GPIO_PTN5, GPIO_PTN6, GPIO_PTN7_RESV,
/* PTO */
GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4,
GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0,
GPIO_PTO0, GPIO_PTO1, GPIO_PTO2, GPIO_PTO3,
GPIO_PTO4, GPIO_PTO5, GPIO_PTO6, GPIO_PTO7,
/* PTP */
GPIO_PTP6, GPIO_PTP5, GPIO_PTP4,
GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0,
GPIO_PTP0, GPIO_PTP1, GPIO_PTP2, GPIO_PTP3,
GPIO_PTP4, GPIO_PTP5, GPIO_PTP6, GPIO_PTP7,
/* PTQ */
GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
GPIO_PTQ0, GPIO_PTQ1, GPIO_PTQ2, GPIO_PTQ3,
GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6, GPIO_PTQ7_RESV,
/* PTR */
GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
GPIO_PTR0, GPIO_PTR1, GPIO_PTR2, GPIO_PTR3,
GPIO_PTR4, GPIO_PTR5, GPIO_PTR6, GPIO_PTR7,
/* PTS */
GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
GPIO_PTS0, GPIO_PTS1, GPIO_PTS2, GPIO_PTS3,
GPIO_PTS4, GPIO_PTS5, GPIO_PTS6, GPIO_PTS7,
/* PTT */
GPIO_PTT5, GPIO_PTT4,
GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
GPIO_PTT0, GPIO_PTT1, GPIO_PTT2, GPIO_PTT3,
GPIO_PTT4, GPIO_PTT5, GPIO_PTT6, GPIO_PTT7,
/* PTU */
GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
GPIO_PTU0, GPIO_PTU1, GPIO_PTU2, GPIO_PTU3,
GPIO_PTU4, GPIO_PTU5, GPIO_PTU6, GPIO_PTU7,
/* PTV */
GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
GPIO_PTV0, GPIO_PTV1, GPIO_PTV2, GPIO_PTV3,
GPIO_PTV4, GPIO_PTV5, GPIO_PTV6, GPIO_PTV7,
/* PTW */
GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
GPIO_PTW0, GPIO_PTW1, GPIO_PTW2, GPIO_PTW3,
GPIO_PTW4, GPIO_PTW5, GPIO_PTW6, GPIO_PTW7,
/* PTX */
GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
GPIO_PTX0, GPIO_PTX1, GPIO_PTX2, GPIO_PTX3,
GPIO_PTX4, GPIO_PTX5, GPIO_PTX6, GPIO_PTX7,
/* PTY */
GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
GPIO_PTY0, GPIO_PTY1, GPIO_PTY2, GPIO_PTY3,
GPIO_PTY4, GPIO_PTY5, GPIO_PTY6, GPIO_PTY7,
/* PTZ */
GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
GPIO_PTZ0, GPIO_PTZ1, GPIO_PTZ2, GPIO_PTZ3,
GPIO_PTZ4, GPIO_PTZ5, GPIO_PTZ6, GPIO_PTZ7,
/* PTA (mobule: LBSC, CPG, LPC) */
/* PTA (mobule: LBSC, RGMII) */
GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY,
GPIO_FN_MD10, GPIO_FN_MD9, GPIO_FN_MD8,
GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO,
GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO,
/* PTB (mobule: LBSC, EtherC, SIM, LPC) */
GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO,
GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO,
GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
GPIO_FN_WPSZ1, GPIO_FN_WPSZ0, GPIO_FN_FWID, GPIO_FN_FLSHSZ,
GPIO_FN_LPC_SPIEN, GPIO_FN_BASEL,
/* PTB (mobule: INTC, ONFI, TMU) */
GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12,
GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8,
GPIO_FN_ON_NRE, GPIO_FN_ON_NWE, GPIO_FN_ON_NWP, GPIO_FN_ON_NCE0,
GPIO_FN_ON_R_B0, GPIO_FN_ON_ALE, GPIO_FN_ON_CLE,
GPIO_FN_TCLK,
/* PTC (mobule: SD) */
GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0,
/* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
/* PTC (mobule: IRQ, PWMU) */
GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4,
GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0,
GPIO_FN_MD6, GPIO_FN_MD5, GPIO_FN_MD3, GPIO_FN_MD2,
GPIO_FN_MD1, GPIO_FN_MD0, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
GPIO_FN_PWMU0, GPIO_FN_PWMU1, GPIO_FN_PWMU2, GPIO_FN_PWMU3,
GPIO_FN_PWMU4, GPIO_FN_PWMU5,
/* PTE (mobule: EtherC) */
GPIO_FN_ET0_CRS_DV, GPIO_FN_ET0_TXD1,
GPIO_FN_ET0_TXD0, GPIO_FN_ET0_TX_EN,
GPIO_FN_ET0_REF_CLK, GPIO_FN_ET0_RXD1,
GPIO_FN_ET0_RXD0, GPIO_FN_ET0_RX_ER,
/* PTD (mobule: SPI0, DMAC) */
GPIO_FN_SP0_MOSI, GPIO_FN_SP0_MISO, GPIO_FN_SP0_SCK,
GPIO_FN_SP0_SCK_FB, GPIO_FN_SP0_SS0, GPIO_FN_SP0_SS1,
GPIO_FN_SP0_SS2, GPIO_FN_SP0_SS3, GPIO_FN_DREQ0,
GPIO_FN_DACK0, GPIO_FN_TEND0,
/* PTF (mobule: EtherC) */
GPIO_FN_ET1_CRS_DV, GPIO_FN_ET1_TXD1,
GPIO_FN_ET1_TXD0, GPIO_FN_ET1_TX_EN,
GPIO_FN_ET1_REF_CLK, GPIO_FN_ET1_RXD1,
GPIO_FN_ET1_RXD0, GPIO_FN_ET1_RX_ER,
/* PTE (mobule: RMII) */
GPIO_FN_RMII0_CRS_DV, GPIO_FN_RMII0_TXD1, GPIO_FN_RMII0_TXD0,
GPIO_FN_RMII0_TXEN, GPIO_FN_RMII0_REFCLK, GPIO_FN_RMII0_RXD1,
GPIO_FN_RMII0_RXD0, GPIO_FN_RMII0_RX_ER,
/* PTG (mobule: SYSTEM, PWMX, LPC) */
GPIO_FN_STATUS0, GPIO_FN_STATUS1,
GPIO_FN_PWX0, GPIO_FN_PWX1, GPIO_FN_PWX2, GPIO_FN_PWX3,
GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD, GPIO_FN_LDRQ,
/* PTF (mobule: RMII, SerMux) */
GPIO_FN_RMII1_CRS_DV, GPIO_FN_RMII1_TXD1, GPIO_FN_RMII1_TXD0,
GPIO_FN_RMII1_TXEN, GPIO_FN_RMII1_REFCLK, GPIO_FN_RMII1_RXD1,
GPIO_FN_RMII1_RXD0, GPIO_FN_RMII1_RX_ER, GPIO_FN_RAC_RI,
/* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
GPIO_FN_TCLK, GPIO_FN_RXD4, GPIO_FN_TXD4,
/* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
GPIO_FN_BOOTFMS, GPIO_FN_BOOTWP,
GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_SERIRQ, GPIO_FN_WDTOVF,
GPIO_FN_LPCPD, GPIO_FN_LDRQ, GPIO_FN_MMCCLK, GPIO_FN_MMCCMD,
/* PTH (mobule: SPI1, LPC, DMAC, ADC) */
GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO,
GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB,
GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1,
GPIO_FN_SP0_SS1,
GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_TEND1, GPIO_FN_DREQ1,
GPIO_FN_DACK1, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
/* PTI (mobule: INTC) */
GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12,
GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8,
/* PTI (mobule: LBSC, SDHI) */
GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0,
/* PTJ (mobule: SCIF234, SERMUX) */
GPIO_FN_RXD3, GPIO_FN_TXD3, GPIO_FN_RXD2, GPIO_FN_TXD2,
GPIO_FN_COM1_TXD, GPIO_FN_COM1_RXD,
GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS,
/* PTJ (mobule: SCIF234) */
GPIO_FN_RTS3, GPIO_FN_CTS3, GPIO_FN_TXD3, GPIO_FN_RXD3,
GPIO_FN_RTS4, GPIO_FN_RXD4, GPIO_FN_TXD4,
/* PTK (mobule: SERMUX) */
GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD,
GPIO_FN_COM2_RTS, GPIO_FN_COM2_CTS,
GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR,
GPIO_FN_COM2_DCD, GPIO_FN_COM2_RI,
/* PTK (mobule: SERMUX, LBSC, SCIF) */
GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD, GPIO_FN_COM2_RTS,
GPIO_FN_COM2_CTS, GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR,
GPIO_FN_COM2_DCD, GPIO_FN_CLKOUT,
GPIO_FN_SCK2, GPIO_FN_SCK4, GPIO_FN_SCK3,
/* PTL (mobule: SERMUX) */
GPIO_FN_RAC_TXD, GPIO_FN_RAC_RXD,
GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS,
GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR,
GPIO_FN_RAC_DCD, GPIO_FN_RAC_RI,
/* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
GPIO_FN_RAC_RXD, GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS,
GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR, GPIO_FN_RAC_DCD,
GPIO_FN_RAC_TXD, GPIO_FN_RXD2, GPIO_FN_CS5,
GPIO_FN_CS6, GPIO_FN_AUDSYNC, GPIO_FN_AUDCK,
GPIO_FN_TXD2,
/* PTM (mobule: IIC, LPC) */
/* PTM (mobule: LBSC, IIC) */
GPIO_FN_CS4, GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_CS0,
GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7,
GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_FMS1,
/* PTN (mobule: SCIF234, EVC) */
GPIO_FN_SCK2, GPIO_FN_RTS4, GPIO_FN_RTS3, GPIO_FN_RTS2,
GPIO_FN_CTS4, GPIO_FN_CTS3, GPIO_FN_CTS2,
GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4,
GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0,
/* PTN (mobule: USB, JMC, SGPIO, WDT) */
GPIO_FN_VBUS_EN, GPIO_FN_VBUS_OC, GPIO_FN_JMCTCK,
GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI,
GPIO_FN_JMCTRST,
GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD, GPIO_FN_SGPIO1_DI,
GPIO_FN_SGPIO1_DO, GPIO_FN_SUB_CLKIN,
/* PTO (mobule: SGPIO) */
GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD,
GPIO_FN_SGPIO0_DI, GPIO_FN_SGPIO0_DO,
GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD,
GPIO_FN_SGPIO1_DI, GPIO_FN_SGPIO1_DO,
/* PTP (mobule: JMC, SCIF234) */
GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI,
GPIO_FN_JMCRST, GPIO_FN_SCK4, GPIO_FN_SCK3,
/* PTO (mobule: SGPIO, SerMux) */
GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD, GPIO_FN_SGPIO0_DI,
GPIO_FN_SGPIO0_DO, GPIO_FN_SGPIO2_CLK, GPIO_FN_SGPIO2_LOAD,
GPIO_FN_SGPIO2_DI, GPIO_FN_SGPIO2_DO, GPIO_FN_COM1_TXD,
GPIO_FN_COM1_RXD, GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS,
/* PTQ (mobule: LPC) */
GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0,
GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK,
/* PTR (mobule: GRA, IIC) */
GPIO_FN_DDC3, GPIO_FN_DDC2,
GPIO_FN_SDA8, GPIO_FN_SCL8, GPIO_FN_SDA2, GPIO_FN_SCL2,
GPIO_FN_DDC3, GPIO_FN_DDC2, GPIO_FN_SDA2, GPIO_FN_SCL2,
GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0,
GPIO_FN_SDA8, GPIO_FN_SCL8,
/* PTS (mobule: GRA, IIC) */
GPIO_FN_DDC1, GPIO_FN_DDC0,
GPIO_FN_SDA9, GPIO_FN_SCL9, GPIO_FN_SDA5, GPIO_FN_SCL5,
GPIO_FN_DDC1, GPIO_FN_DDC0, GPIO_FN_SDA5, GPIO_FN_SCL5,
GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3,
GPIO_FN_SDA9, GPIO_FN_SCL9,
/* PTT (mobule: SYSTEM, PWMX) */
GPIO_FN_AUDSYNC, GPIO_FN_AUDCK,
GPIO_FN_AUDATA3, GPIO_FN_AUDATA2,
GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
GPIO_FN_PWX7, GPIO_FN_PWX6, GPIO_FN_PWX5, GPIO_FN_PWX4,
/* PTT (mobule: PWMX, AUD) */
GPIO_FN_PWMX7, GPIO_FN_PWMX6, GPIO_FN_PWMX5, GPIO_FN_PWMX4,
GPIO_FN_PWMX3, GPIO_FN_PWMX2, GPIO_FN_PWMX1, GPIO_FN_PWMX0,
GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1,
GPIO_FN_AUDATA0, GPIO_FN_STATUS1, GPIO_FN_STATUS0,
/* PTU (mobule: LBSC, DMAC) */
GPIO_FN_CS6, GPIO_FN_CS5, GPIO_FN_CS4, GPIO_FN_CS0,
GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_A25, GPIO_FN_A24,
GPIO_FN_DREQ0, GPIO_FN_DACK0,
/* PTU (mobule: LPC, APM) */
GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
GPIO_FN_APMONCTL_O, GPIO_FN_APMPWBTOUT_O, GPIO_FN_APMSCI_O,
GPIO_FN_APMVDDON, GPIO_FN_APMSLPBTN, GPIO_FN_APMPWRBTN,
GPIO_FN_APMS5N, GPIO_FN_APMS3N,
/* PTV (mobule: LBSC, DMAC) */
/* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
GPIO_FN_TEND0, GPIO_FN_DREQ1, GPIO_FN_DACK1, GPIO_FN_TEND1,
GPIO_FN_COM2_RI, GPIO_FN_R_SPI_MOSI, GPIO_FN_R_SPI_MISO,
GPIO_FN_R_SPI_RSPCK, GPIO_FN_R_SPI_SSL0, GPIO_FN_R_SPI_SSL1,
GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_VBIOS_DI,
GPIO_FN_VBIOS_DO, GPIO_FN_VBIOS_CLK, GPIO_FN_VBIOS_CS,
/* PTW (mobule: LBSC) */
/* PTW (mobule: LBSC, EVC, SCIF) */
GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
GPIO_FN_EVENT5, GPIO_FN_EVENT4, GPIO_FN_EVENT3, GPIO_FN_EVENT2,
GPIO_FN_EVENT1, GPIO_FN_EVENT0, GPIO_FN_CTS4, GPIO_FN_CTS2,
/* PTX (mobule: LBSC) */
/* PTX (mobule: LBSC, SCIF, SIM) */
GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
GPIO_FN_RTS2, GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
/* PTY (mobule: LBSC) */
GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
/* PTZ (mobule: eMMC, ONFI) */
GPIO_FN_MMCDAT7, GPIO_FN_MMCDAT6, GPIO_FN_MMCDAT5,
GPIO_FN_MMCDAT4, GPIO_FN_MMCDAT3, GPIO_FN_MMCDAT2,
GPIO_FN_MMCDAT1, GPIO_FN_MMCDAT0,
GPIO_FN_ON_DQ7, GPIO_FN_ON_DQ6, GPIO_FN_ON_DQ5, GPIO_FN_ON_DQ4,
GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0,
};
#endif /* __ASM_SH7757_H__ */

64
arch/sh/include/cpu-sh4/cpu/shx3.h 100644
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@ -0,0 +1,64 @@
#ifndef __CPU_SHX3_H
#define __CPU_SHX3_H
enum {
/* PA */
GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
/* PB */
GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
/* PC */
GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
/* PD */
GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
/* PE */
GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4,
GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
/* PF */
GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
/* PG */
GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
/* PH */
GPIO_PH5, GPIO_PH4,
GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
/* SCIF */
GPIO_FN_SCK3, GPIO_FN_TXD3, GPIO_FN_RXD3,
GPIO_FN_SCK2, GPIO_FN_TXD2, GPIO_FN_RXD2,
GPIO_FN_SCK1, GPIO_FN_TXD1, GPIO_FN_RXD1,
GPIO_FN_SCK0, GPIO_FN_TXD0, GPIO_FN_RXD0,
/* LBSC */
GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
GPIO_FN_WE3, GPIO_FN_WE2, GPIO_FN_CS6, GPIO_FN_CS5,
GPIO_FN_CS4, GPIO_FN_CLKOUTENB, GPIO_FN_BREQ,
GPIO_FN_IOIS16, GPIO_FN_CE2B, GPIO_FN_CE2A, GPIO_FN_BACK,
/* DMAC */
GPIO_FN_DACK0, GPIO_FN_DREQ0, GPIO_FN_DRAK0,
GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DRAK1,
GPIO_FN_DACK2, GPIO_FN_DREQ2, GPIO_FN_DRAK2,
GPIO_FN_DACK3, GPIO_FN_DREQ3, GPIO_FN_DRAK3,
/* INTC */
GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0,
GPIO_FN_IRL3, GPIO_FN_IRL2, GPIO_FN_IRL1, GPIO_FN_IRL0,
GPIO_FN_IRQOUT, GPIO_FN_STATUS1, GPIO_FN_STATUS0,
};
#endif /* __CPU_SHX3_H */

117
arch/sh/include/mach-common/mach/sh2007.h 100644
View File

@ -0,0 +1,117 @@
#ifndef __MACH_SH2007_H
#define __MACH_SH2007_H
#define CS5BCR 0xff802050
#define CS5WCR 0xff802058
#define CS5PCR 0xff802070
#define BUS_SZ8 1
#define BUS_SZ16 2
#define BUS_SZ32 3
#define PCMCIA_IODYN 1
#define PCMCIA_ATA 0
#define PCMCIA_IO8 2
#define PCMCIA_IO16 3
#define PCMCIA_COMM8 4
#define PCMCIA_COMM16 5
#define PCMCIA_ATTR8 6
#define PCMCIA_ATTR16 7
#define TYPE_SRAM 0
#define TYPE_PCMCIA 4
/* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
#define IWW5 0
#define IWW6 3
/* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
#define IWRWD5 2
#define IWRWD6 2
/* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
#define IWRWS5 2
#define IWRWS6 2
/* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
#define IWRRD5 2
#define IWRRD6 2
/* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
#define IWRRS5 0
#define IWRRS6 2
/* burst count (0-3:4,8,16,32) */
#define BST5 0
#define BST6 0
/* bus size */
#define SZ5 BUS_SZ16
#define SZ6 BUS_SZ16
/* RD hold for SRAM (0-1:0,1) */
#define RDSPL5 0
#define RDSPL6 0
/* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
#define BW5 0
#define BW6 0
/* Multiplex (0-1:0,1) */
#define MPX5 0
#define MPX6 0
/* device type */
#define TYPE5 TYPE_PCMCIA
#define TYPE6 TYPE_PCMCIA
/* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
#define ADS5 0
#define ADS6 0
/* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
#define ADH5 0
#define ADH6 0
/* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
#define RDS5 0
#define RDS6 0
/* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
#define RDH5 0
#define RDH6 0
/* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
#define WTS5 0
#define WTS6 0
/* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
#define WTH5 0
#define WTH6 0
/* BS hold (0-1:1,2) */
#define BSH5 0
#define BSH6 0
/* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
#define IW5 6 /* 60ns PIO mode 4 */
#define IW6 15 /* 250ns */
#define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */
#define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */
#define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */
#define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */
/* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
#define PCIW5 12
/* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */
#define TEDA5 2
/* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */
#define TEDB5 4
/* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */
#define TEHA5 2
/* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */
#define TEHB5 3
#define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \
(IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \
(SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5)
#define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \
(RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5)
#define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \
(PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \
(TEDB5<<8)|(TEHA5<<4)|TEHB5)
#define SMC0_BASE 0xb0800000 /* eth0 */
#define SMC1_BASE 0xb0900000 /* eth1 */
#define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */
#define IDE_BASE 0xb4000000 /* IDE */
#define PC104_IO_BASE 0xb8000000
#define PC104_MEM_BASE 0xba000000
#define SMC_IO_SIZE 0x100
#define CF_OFFSET 0x1f0
#define IDE_OFFSET 0x170
#endif /* __MACH_SH2007_H */

26
arch/sh/include/mach-sdk7786/mach/fpga.h
View File

@ -31,11 +31,35 @@
#define EXTASR 0x110
#define SPCAR 0x120
#define INTMSR 0x130
#define PCIECR 0x140
#define PCIECR_PCIEMUX1 BIT(15)
#define PCIECR_PCIEMUX0 BIT(14)
#define PCIECR_PRST4 BIT(12) /* slot 4 card present */
#define PCIECR_PRST3 BIT(11) /* slot 3 card present */
#define PCIECR_PRST2 BIT(10) /* slot 2 card present */
#define PCIECR_PRST1 BIT(9) /* slot 1 card present */
#define PCIECR_CLKEN BIT(4) /* oscillator enable */
#define FAER 0x150
#define USRGPIR 0x160
/* 0x170 reserved */
#define LCLASR 0x180
#define LCLASR 0x180
#define LCLASR_FRAMEN BIT(15)
#define LCLASR_FPGA_SEL_SHIFT 12
#define LCLASR_NAND_SEL_SHIFT 8
#define LCLASR_NORB_SEL_SHIFT 4
#define LCLASR_NORA_SEL_SHIFT 0
#define LCLASR_AREA_MASK 0x7
#define LCLASR_FPGA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT)
#define LCLASR_NAND_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT)
#define LCLASR_NORB_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT)
#define LCLASR_NORA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT)
#define SBCR 0x190
#define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */

12
arch/sh/include/mach-x3proto/mach/hardware.h 100644
View File

@ -0,0 +1,12 @@
#ifndef __MACH_X3PROTO_HARDWARE_H
#define __MACH_X3PROTO_HARDWARE_H
struct gpio_chip;
/* arch/sh/boards/mach-x3proto/gpio.c */
int x3proto_gpio_setup(void);
extern struct gpio_chip x3proto_gpio_chip;
#define NR_BASEBOARD_GPIOS 16
#endif /* __MACH_X3PROTO_HARDWARE_H */

0
arch/sh/include/asm/ilsel.h → arch/sh/include/mach-x3proto/mach/ilsel.h
View File

8
arch/sh/kernel/Makefile
View File

@ -12,9 +12,9 @@ endif
CFLAGS_REMOVE_return_address.o = -pg
obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \
idle.o io.o irq.o \
irq_$(BITS).o machvec.o nmi_debug.o process.o \
process_$(BITS).o ptrace_$(BITS).o \
idle.o io.o irq.o irq_$(BITS).o kdebugfs.o \
machvec.o nmi_debug.o process.o \
process_$(BITS).o ptrace.o ptrace_$(BITS).o \
reboot.o return_address.o \
setup.o signal_$(BITS).o sys_sh.o sys_sh$(BITS).o \
syscalls_$(BITS).o time.o topology.o traps.o \
@ -44,4 +44,4 @@ obj-$(CONFIG_HAS_IOPORT) += io_generic.o
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
EXTRA_CFLAGS += -Werror
ccflags-y := -Werror

4
arch/sh/kernel/clkdev.c
View File

@ -161,9 +161,11 @@ EXPORT_SYMBOL(clk_add_alias);
*/
void clkdev_drop(struct clk_lookup *cl)
{
struct clk_lookup_alloc *cla = container_of(cl, struct clk_lookup_alloc, cl);
mutex_lock(&clocks_mutex);
list_del(&cl->node);
mutex_unlock(&clocks_mutex);
kfree(cl);
kfree(cla);
}
EXPORT_SYMBOL(clkdev_drop);

2
arch/sh/kernel/cpu/sh4/probe.c
View File

@ -150,7 +150,7 @@ void __cpuinit cpu_probe(void)
boot_cpu_data.type = CPU_SH7724;
boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
break;
case 0x50:
case 0x10:
boot_cpu_data.type = CPU_SH7757;
break;
}

5
arch/sh/kernel/cpu/sh4a/Makefile
View File

@ -8,13 +8,13 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o
obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o
obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o
# SMP setup
smp-$(CONFIG_CPU_SHX3) := smp-shx3.o
@ -40,6 +40,7 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
pinmux-$(CONFIG_CPU_SUBTYPE_SHX3) := pinmux-shx3.o
obj-y += $(clock-y)
obj-$(CONFIG_SMP) += $(smp-y)

235
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
View File

@ -3,7 +3,7 @@
*
* SH7757 support for the clock framework
*
* Copyright (C) 2009 Renesas Solutions Corp.
* Copyright (C) 2009-2010 Renesas Solutions Corp.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
@ -16,124 +16,147 @@
#include <asm/clock.h>
#include <asm/freq.h>
static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
16, 1, 1, 32, 1, 1, 1, 1 };
static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
16, 1, 1, 32, 1, 1, 1, 1 };
static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
16, 1, 1, 32, 1, 1, 1, 1 };
static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
16, 1, 1, 32, 1, 1, 1, 1 };
static void master_clk_init(struct clk *clk)
{
clk->rate = CONFIG_SH_PCLK_FREQ * 16;
}
static struct clk_ops sh7757_master_clk_ops = {
.init = master_clk_init,
};
static void module_clk_recalc(struct clk *clk)
{
int idx = __raw_readl(FRQCR) & 0x0000000f;
clk->rate = clk->parent->rate / p1fc_divisors[idx];
}
static struct clk_ops sh7757_module_clk_ops = {
.recalc = module_clk_recalc,
};
static void bus_clk_recalc(struct clk *clk)
{
int idx = (__raw_readl(FRQCR) >> 8) & 0x0000000f;
clk->rate = clk->parent->rate / bfc_divisors[idx];
}
static struct clk_ops sh7757_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
static void cpu_clk_recalc(struct clk *clk)
{
int idx = (__raw_readl(FRQCR) >> 20) & 0x0000000f;
clk->rate = clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7757_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
};
static struct clk_ops *sh7757_clk_ops[] = {
&sh7757_master_clk_ops,
&sh7757_module_clk_ops,
&sh7757_bus_clk_ops,
&sh7757_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
{
if (idx < ARRAY_SIZE(sh7757_clk_ops))
*ops = sh7757_clk_ops[idx];
}
static void shyway_clk_recalc(struct clk *clk)
{
int idx = (__raw_readl(FRQCR) >> 12) & 0x0000000f;
clk->rate = clk->parent->rate / sfc_divisors[idx];
}
static struct clk_ops sh7757_shyway_clk_ops = {
.recalc = shyway_clk_recalc,
};
static struct clk sh7757_shyway_clk = {
.flags = CLK_ENABLE_ON_INIT,
.ops = &sh7757_shyway_clk_ops,
};
/*
* Additional sh7757-specific on-chip clocks that aren't already part of the
* clock framework
* Default rate for the root input clock, reset this with clk_set_rate()
* from the platform code.
*/
static struct clk *sh7757_onchip_clocks[] = {
&sh7757_shyway_clk,
static struct clk extal_clk = {
.rate = 48000000,
};
static unsigned long pll_recalc(struct clk *clk)
{
int multiplier;
multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
return clk->parent->rate * multiplier;
}
static struct clk_ops pll_clk_ops = {
.recalc = pll_recalc,
};
static struct clk pll_clk = {
.ops = &pll_clk_ops,
.parent = &extal_clk,
.flags = CLK_ENABLE_ON_INIT,
};
static struct clk *clks[] = {
&extal_clk,
&pll_clk,
};
static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
1, 1, 1, 16, 1, 24, 1, 1 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = div2,
.nr_divisors = ARRAY_SIZE(div2),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
};
enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
#define DIV4(_bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
struct clk div4_clks[DIV4_NR] = {
/*
* P clock is always enable, because some P clock modules is used
* by Host PC.
*/
[DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
[DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
};
#define MSTPCR0 0xffc80030
#define MSTPCR1 0xffc80034
enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112,
MSTP111, MSTP110, MSTP103, MSTP102,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
/* MSTPCR0 */
[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
/* MSTPCR1 */
[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
[MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
[MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
[MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
[MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
/* MSTP32 clocks */
CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]),
CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]),
{
/* TMU0 */
.dev_id = "sh_tmu.0",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP113],
}, {
/* TMU1 */
.dev_id = "sh_tmu.1",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP114],
},
{
/* SCIF4 (But, ID is 2) */
.dev_id = "sh-sci.2",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP112],
}, {
/* SCIF3 */
.dev_id = "sh-sci.1",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP111],
}, {
/* SCIF2 */
.dev_id = "sh-sci.0",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP110],
},
CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
};
static int __init sh7757_clk_init(void)
int __init arch_clk_init(void)
{
struct clk *clk = clk_get(NULL, "master_clk");
int i;
int i, ret = 0;
for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) {
struct clk *clkp = sh7757_onchip_clocks[i];
for (i = 0; i < ARRAY_SIZE(clks); i++)
ret |= clk_register(clks[i]);
for (i = 0; i < ARRAY_SIZE(lookups); i++)
clkdev_add(&lookups[i]);
clkp->parent = clk;
clk_register(clkp);
clk_enable(clkp);
}
if (!ret)
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
&div4_table);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
/*
* Now that we have the rest of the clocks registered, we need to
* force the parent clock to propagate so that these clocks will
* automatically figure out their rate. We cheat by handing the
* parent clock its current rate and forcing child propagation.
*/
clk_set_rate(clk, clk_get_rate(clk));
clk_put(clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
return 0;
return ret;
}
arch_initcall(sh7757_clk_init);

259
arch/sh/kernel/cpu/sh4a/clock-shx3.c
View File

@ -5,7 +5,7 @@
*
* Copyright (C) 2006-2007 Renesas Technology Corp.
* Copyright (C) 2006-2007 Renesas Solutions Corp.
* Copyright (C) 2006-2007 Paul Mundt
* Copyright (C) 2006-2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
@ -18,120 +18,179 @@
#include <asm/clock.h>
#include <asm/freq.h>
static int ifc_divisors[] = { 1, 2, 4 ,6 };
static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 };
static int cfc_divisors[] = { 1, 1, 4, 6 };
#define IFC_POS 28
#define IFC_MSK 0x0003
#define BFC_MSK 0x000f
#define PFC_MSK 0x000f
#define CFC_MSK 0x0003
#define BFC_POS 16
#define PFC_POS 0
#define CFC_POS 20
static void master_clk_init(struct clk *clk)
{
clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];
}
static struct clk_ops shx3_master_clk_ops = {
.init = master_clk_init,
};
static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK);
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops shx3_module_clk_ops = {
.recalc = module_clk_recalc,
};
static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK);
return clk->parent->rate / bfc_divisors[idx];
}
static struct clk_ops shx3_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);
return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops shx3_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
};
static struct clk_ops *shx3_clk_ops[] = {
&shx3_master_clk_ops,
&shx3_module_clk_ops,
&shx3_bus_clk_ops,
&shx3_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
{
if (idx < ARRAY_SIZE(shx3_clk_ops))
*ops = shx3_clk_ops[idx];
}
static unsigned long shyway_clk_recalc(struct clk *clk)
{
int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);
return clk->parent->rate / cfc_divisors[idx];
}
static struct clk_ops shx3_shyway_clk_ops = {
.recalc = shyway_clk_recalc,
};
static struct clk shx3_shyway_clk = {
.flags = CLK_ENABLE_ON_INIT,
.ops = &shx3_shyway_clk_ops,
};
/*
* Additional SHx3-specific on-chip clocks that aren't already part of the
* clock framework
* Default rate for the root input clock, reset this with clk_set_rate()
* from the platform code.
*/
static struct clk *shx3_onchip_clocks[] = {
&shx3_shyway_clk,
static struct clk extal_clk = {
.rate = 16666666,
};
static unsigned long pll_recalc(struct clk *clk)
{
/* PLL1 has a fixed x72 multiplier. */
return clk->parent->rate * 72;
}
static struct clk_ops pll_clk_ops = {
.recalc = pll_recalc,
};
static struct clk pll_clk = {
.ops = &pll_clk_ops,
.parent = &extal_clk,
.flags = CLK_ENABLE_ON_INIT,
};
static struct clk *clks[] = {
&extal_clk,
&pll_clk,
};
static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
24, 32, 36, 48 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = div2,
.nr_divisors = ARRAY_SIZE(div2),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
};
enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR };
#define DIV4(_bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
struct clk div4_clks[DIV4_NR] = {
[DIV4_P] = DIV4(0, 0x0f80, 0),
[DIV4_SHA] = DIV4(4, 0x0ff0, 0),
[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
};
#define MSTPCR0 0xffc00030
#define MSTPCR1 0xffc00034
enum { MSTP027, MSTP026, MSTP025, MSTP024,
MSTP009, MSTP008, MSTP003, MSTP002,
MSTP001, MSTP000, MSTP119, MSTP105,
MSTP104, MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
/* MSTPCR0 */
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
[MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
/* MSTPCR1 */
[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
};
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
/* MSTP32 clocks */
{
/* SCIF3 */
.dev_id = "sh-sci.3",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP027],
}, {
/* SCIF2 */
.dev_id = "sh-sci.2",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP026],
}, {
/* SCIF1 */
.dev_id = "sh-sci.1",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP025],
}, {
/* SCIF0 */
.dev_id = "sh-sci.0",
.con_id = "sci_fck",
.clk = &mstp_clks[MSTP024],
},
CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
{
/* TMU0 */
.dev_id = "sh_tmu.0",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP008],
}, {
/* TMU1 */
.dev_id = "sh_tmu.1",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP008],
}, {
/* TMU2 */
.dev_id = "sh_tmu.2",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP008],
}, {
/* TMU3 */
.dev_id = "sh_tmu.3",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP009],
}, {
/* TMU4 */
.dev_id = "sh_tmu.4",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP009],
}, {
/* TMU5 */
.dev_id = "sh_tmu.5",
.con_id = "tmu_fck",
.clk = &mstp_clks[MSTP009],
},
CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
};
int __init arch_clk_init(void)
{
struct clk *clk;
int i, ret = 0;
cpg_clk_init();
for (i = 0; i < ARRAY_SIZE(clks); i++)
ret |= clk_register(clks[i]);
for (i = 0; i < ARRAY_SIZE(lookups); i++)
clkdev_add(&lookups[i]);
clk = clk_get(NULL, "master_clk");
for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
struct clk *clkp = shx3_onchip_clocks[i];
clkp->parent = clk;
ret |= clk_register(clkp);
}
clk_put(clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
&div4_table);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
return ret;
}

34
arch/sh/kernel/cpu/sh4a/intc-shx3.c 100644
View File

@ -0,0 +1,34 @@
/*
* Shared support for SH-X3 interrupt controllers.
*
* Copyright (C) 2009 - 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/init.h>
#define INTACK 0xfe4100b8
#define INTACKCLR 0xfe4100bc
#define INTC_USERIMASK 0xfe411000
#ifdef CONFIG_INTC_BALANCING
unsigned int irq_lookup(unsigned int irq)
{
return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
}
void irq_finish(unsigned int irq)
{
__raw_writel(irq2evt(irq), INTACKCLR);
}
#endif
static int __init shx3_irq_setup(void)
{
return register_intc_userimask(INTC_USERIMASK);
}
arch_initcall(shx3_irq_setup);

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