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arm64: dts: NS2: Add all of the UARTs 

Add all of the UARTs present on NS2 and enable them in the SVK device
tree file.  Also, do some magic to make sure that uart3 is discovered as
ttyS0 (as that is the console UART).

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
hifive-unleashed-5.1
Jon Mason 2016-05-11 18:56:08 -04:00 committed by Florian Fainelli
parent 5f2fb24141
commit 1e0fdee81e
2 changed files with 46 additions and 0 deletions
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16
arch/arm64/boot/dts/broadcom/ns2-svk.dts
View File

@ -40,10 +40,14 @@
aliases {
serial0 = &uart3;
serial1 = &uart0;
serial2 = &uart1;
serial3 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs = "earlycon=uart8250,mmio32,0x66130000";
};
memory {
@ -68,6 +72,18 @@
status = "ok";
};
&uart0 {
status = "ok";
};
&uart1 {
status = "ok";
};
&uart2 {
status = "ok";
};
&uart3 {
status = "ok";
};

30
arch/arm64/boot/dts/broadcom/ns2.dtsi
View File

@ -357,6 +357,36 @@
status = "disabled";
};
uart0: serial@66100000 {
compatible = "snps,dw-apb-uart";
reg = <0x66100000 0x100>;
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@66110000 {
compatible = "snps,dw-apb-uart";
reg = <0x66110000 0x100>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@66120000 {
compatible = "snps,dw-apb-uart";
reg = <0x66120000 0x100>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@66130000 {
compatible = "snps,dw-apb-uart";
reg = <0x66130000 0x100>;