ARM: at91/dt: Declare a second ram controller when relevant
The G45 and 9263 SoCs has two identical ram controller, that are defined as a single node, with two reg cells. The proper way to support such a case is to have two separate DT nodes. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>hifive-unleashed-5.1
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7e94834600
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1e165a7dc2
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@ -71,10 +71,14 @@
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reg = <0xfffffc00 0x100>;
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};
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ramc: ramc@ffffe200 {
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ramc0: ramc@ffffe200 {
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compatible = "atmel,at91sam9260-sdramc";
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reg = <0xffffe200 0x200
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0xffffe800 0x200>;
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reg = <0xffffe200 0x200>;
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};
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ramc1: ramc@ffffe800 {
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compatible = "atmel,at91sam9260-sdramc";
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reg = <0xffffe800 0x200>;
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};
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pit: timer@fffffd30 {
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@ -75,8 +75,12 @@
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ramc0: ramc@ffffe400 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffe400 0x200
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0xffffe600 0x200>;
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reg = <0xffffe400 0x200>;
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};
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ramc1: ramc@ffffe600 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffe600 0x200>;
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};
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pmc: pmc@fffffc00 {
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