powerpc: gpio driver for mpc8349/8572/8610 and compatible
Structured similar to the existing QE GPIO support. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>hifive-unleashed-5.1
Peter Korsgaard
Kumar Gala
parent
1afb7f809b
commit
1e16dfc1ba
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@ -0,0 +1,40 @@
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GPIO controllers on MPC8xxx SoCs
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This is for the non-QE/CPM/GUTs GPIO controllers as found on
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8349, 8572, 8610 and compatible.
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Every GPIO controller node must have #gpio-cells property defined,
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this information will be used to translate gpio-specifiers.
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Required properties:
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- compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for
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83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters (currently unused).
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- interrupts : Interrupt mapping for GPIO IRQ (currently unused).
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- interrupt-parent : Phandle for the interrupt controller that
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services interrupts for this device.
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- gpio-controller : Marks the port as GPIO controller.
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Example of gpio-controller nodes for a MPC8347 SoC:
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gpio1: gpio-controller@c00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
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reg = <0xc00 0x100>;
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interrupts = <74 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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};
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gpio2: gpio-controller@d00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
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reg = <0xd00 0x100>;
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interrupts = <75 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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};
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See booting-without-of.txt for details of how to specify GPIO
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information for devices.
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@ -7,6 +7,15 @@ config PPC4xx_PCI_EXPRESS
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depends on PCI && 4xx
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default n
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config MPC8xxx_GPIO
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bool "MPC8xxx GPIO support"
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depends on PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || PPC_85xx || PPC_86xx
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select GENERIC_GPIO
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select ARCH_REQUIRE_GPIOLIB
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help
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Say Y here if you're going to use hardware that connects to the
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MPC831x/834x/837x/8572/8610 GPIOs.
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config PPC_MSI_BITMAP
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bool
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depends on PCI_MSI
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@ -16,6 +16,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
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obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
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obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
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obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
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obj-$(CONFIG_RAPIDIO) += fsl_rio.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
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@ -0,0 +1,171 @@
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/*
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* GPIOs on MPC8349/8572/8610 and compatible
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*
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* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/gpio.h>
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#define MPC8XXX_GPIO_PINS 32
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#define GPIO_DIR 0x00
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#define GPIO_ODR 0x04
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#define GPIO_DAT 0x08
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#define GPIO_IER 0x0c
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#define GPIO_IMR 0x10
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#define GPIO_ICR 0x14
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struct mpc8xxx_gpio_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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/*
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* shadowed data register to be able to clear/set output pins in
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* open drain mode safely
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*/
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u32 data;
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};
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static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
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{
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return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
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}
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static inline struct mpc8xxx_gpio_chip *
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to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
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{
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return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
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}
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static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
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}
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static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
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}
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static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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if (val)
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mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
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else
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mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
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out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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return 0;
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}
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static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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unsigned long flags;
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mpc8xxx_gpio_set(gc, gpio, val);
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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return 0;
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}
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static void __init mpc8xxx_add_controller(struct device_node *np)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct of_gpio_chip *of_gc;
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struct gpio_chip *gc;
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int ret;
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mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
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if (!mpc8xxx_gc) {
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ret = -ENOMEM;
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goto err;
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}
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spin_lock_init(&mpc8xxx_gc->lock);
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mm_gc = &mpc8xxx_gc->mm_gc;
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of_gc = &mm_gc->of_gc;
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gc = &of_gc->gc;
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mm_gc->save_regs = mpc8xxx_gpio_save_regs;
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of_gc->gpio_cells = 2;
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gc->ngpio = MPC8XXX_GPIO_PINS;
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gc->direction_input = mpc8xxx_gpio_dir_in;
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gc->direction_output = mpc8xxx_gpio_dir_out;
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gc->get = mpc8xxx_gpio_get;
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gc->set = mpc8xxx_gpio_set;
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ret = of_mm_gpiochip_add(np, mm_gc);
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if (ret)
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goto err;
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return;
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err:
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pr_err("%s: registration failed with status %d\n",
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np->full_name, ret);
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kfree(mpc8xxx_gc);
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return;
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}
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static int __init mpc8xxx_add_gpiochips(void)
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{
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struct device_node *np;
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for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio")
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mpc8xxx_add_controller(np);
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for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio")
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mpc8xxx_add_controller(np);
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for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio")
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mpc8xxx_add_controller(np);
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return 0;
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}
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arch_initcall(mpc8xxx_add_gpiochips);
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