ARM: EXYNOS: Add irq_domain support for interrupt combiner
Add irq_domain support for hardware interrupts of the interrupt combiner. The hardware interrupts of all the instances of the combiner are grouped in a single irq_domain. Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -19,6 +19,8 @@
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#include <linux/serial_core.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/export.h>
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#include <linux/irqdomain.h>
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#include <asm/proc-fns.h>
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#include <asm/exception.h>
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@ -399,6 +401,7 @@ struct combiner_chip_data {
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void __iomem *base;
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};
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static struct irq_domain *combiner_irq_domain;
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static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
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static inline void __iomem *combiner_base(struct irq_data *data)
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@ -411,14 +414,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
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static void combiner_mask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->irq % 32);
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
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}
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static void combiner_unmask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->irq % 32);
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
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}
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@ -474,36 +477,58 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
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irq_set_chained_handler(irq, combiner_handle_cascade_irq);
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}
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static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
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unsigned int irq_start)
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static void __init combiner_init_one(unsigned int combiner_nr,
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void __iomem *base)
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{
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unsigned int i;
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unsigned int max_nr;
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if (soc_is_exynos5250())
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max_nr = EXYNOS5_MAX_COMBINER_NR;
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else
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max_nr = EXYNOS4_MAX_COMBINER_NR;
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if (combiner_nr >= max_nr)
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BUG();
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combiner_data[combiner_nr].base = base;
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combiner_data[combiner_nr].irq_offset = irq_start;
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combiner_data[combiner_nr].irq_offset = irq_find_mapping(
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combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
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combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
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/* Disable all interrupts */
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__raw_writel(combiner_data[combiner_nr].irq_mask,
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base + COMBINER_ENABLE_CLEAR);
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}
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/* Setup the Linux IRQ subsystem */
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static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
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irq_set_chip_data(irq, &combiner_data[hw >> 3]);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
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+ MAX_IRQ_IN_COMBINER; i++) {
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irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
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irq_set_chip_data(i, &combiner_data[combiner_nr]);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops combiner_irq_domain_ops = {
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.map = combiner_irq_domain_map,
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};
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void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
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{
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int i, irq_base;
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unsigned int max_nr, nr_irq;
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max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
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EXYNOS4_MAX_COMBINER_NR;
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nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
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irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
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if (IS_ERR_VALUE(irq_base)) {
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irq_base = COMBINER_IRQ(0, 0);
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pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
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}
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combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
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&combiner_irq_domain_ops, &combiner_data);
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if (WARN_ON(!combiner_irq_domain)) {
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pr_warning("%s: irq domain init failed\n", __func__);
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return;
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}
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for (i = 0; i < max_nr; i++) {
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combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
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combiner_cascade_irq(i, IRQ_SPI(i));
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}
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}
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@ -516,7 +541,6 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
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void __init exynos4_init_irq(void)
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{
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int irq;
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unsigned int gic_bank_offset;
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gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
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@ -528,12 +552,7 @@ void __init exynos4_init_irq(void)
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of_irq_init(exynos4_dt_irq_match);
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#endif
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for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
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combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
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COMBINER_IRQ(irq, 0));
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combiner_cascade_irq(irq, IRQ_SPI(irq));
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}
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combiner_init(S5P_VA_COMBINER_BASE, NULL);
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/*
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* The parameters of s5p_init_irq() are for VIC init.
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@ -545,17 +564,10 @@ void __init exynos4_init_irq(void)
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void __init exynos5_init_irq(void)
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{
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int irq;
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#ifdef CONFIG_OF
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of_irq_init(exynos4_dt_irq_match);
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#endif
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for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
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combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
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COMBINER_IRQ(irq, 0));
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combiner_cascade_irq(irq, IRQ_SPI(irq));
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}
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combiner_init(S5P_VA_COMBINER_BASE, NULL);
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/*
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* The parameters of s5p_init_irq() are for VIC init.
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