[PATCH] e1000: Added interrupt auto mask support
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: John Ronciak <john.ronciak@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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@ -1736,10 +1736,15 @@ e1000_configure_rx(struct e1000_adapter *adapter)
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}
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if (hw->mac_type >= e1000_82571) {
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/* Reset delay timers after every interrupt */
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ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
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/* Reset delay timers after every interrupt */
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ctrl_ext |= E1000_CTRL_EXT_CANC;
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#ifdef CONFIG_E1000_NAPI
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/* Auto-Mask interrupts upon ICR read. */
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ctrl_ext |= E1000_CTRL_EXT_IAME;
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#endif
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E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
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E1000_WRITE_REG(hw, IAM, ~0);
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E1000_WRITE_FLUSH(hw);
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}
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@ -3244,12 +3249,24 @@ e1000_intr(int irq, void *data, struct pt_regs *regs)
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struct e1000_adapter *adapter = netdev_priv(netdev);
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struct e1000_hw *hw = &adapter->hw;
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uint32_t icr = E1000_READ_REG(hw, ICR);
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#if defined(CONFIG_E1000_NAPI) && defined(CONFIG_E1000_MQ) || !defined(CONFIG_E1000_NAPI)
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#ifndef CONFIG_E1000_NAPI
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int i;
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#else
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/* Interrupt Auto-Mask...upon reading ICR,
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* interrupts are masked. No need for the
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* IMC write, but it does mean we should
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* account for it ASAP. */
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if (likely(hw->mac_type >= e1000_82571))
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atomic_inc(&adapter->irq_sem);
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#endif
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if(unlikely(!icr))
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if (unlikely(!icr)) {
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#ifdef CONFIG_E1000_NAPI
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if (hw->mac_type >= e1000_82571)
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e1000_irq_enable(adapter);
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#endif
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return IRQ_NONE; /* Not our interrupt */
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}
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if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
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hw->get_link_status = 1;
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@ -3257,9 +3274,11 @@ e1000_intr(int irq, void *data, struct pt_regs *regs)
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}
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#ifdef CONFIG_E1000_NAPI
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atomic_inc(&adapter->irq_sem);
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E1000_WRITE_REG(hw, IMC, ~0);
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E1000_WRITE_FLUSH(hw);
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if (unlikely(hw->mac_type < e1000_82571)) {
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atomic_inc(&adapter->irq_sem);
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E1000_WRITE_REG(hw, IMC, ~0);
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E1000_WRITE_FLUSH(hw);
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}
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#ifdef CONFIG_E1000_MQ
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if (atomic_read(&adapter->rx_sched_call_data.count) == 0) {
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/* We must setup the cpumask once count == 0 since
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