KVM: x86: Misc LAPIC changes to expose helper functions
Exporting LAPIC utility functions and macros for re-use in SVM code. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Reviewed-by: Radim Krčmář <rkrcmar@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>hifive-unleashed-5.1
Suravee Suthikulpanit
Paolo Bonzini
parent
2086d3200d
commit
1e6e2755b6
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@ -59,9 +59,8 @@
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/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
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#define apic_debug(fmt, arg...)
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#define APIC_LVT_NUM 6
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/* 14 is the version for Xeon and Pentium 8.4.8*/
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#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
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#define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
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#define LAPIC_MMIO_LENGTH (1 << 12)
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/* followed define is not in apicdef.h */
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#define APIC_SHORT_MASK 0xc0000
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@ -73,14 +72,6 @@
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#define APIC_BROADCAST 0xFF
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#define X2APIC_BROADCAST 0xFFFFFFFFul
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#define VEC_POS(v) ((v) & (32 - 1))
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#define REG_POS(v) (((v) >> 5) << 4)
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static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
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{
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*((u32 *) (apic->regs + reg_off)) = val;
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}
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static inline int apic_test_vector(int vec, void *bitmap)
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{
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return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
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@ -94,11 +85,6 @@ bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
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apic_test_vector(vector, apic->regs + APIC_IRR);
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}
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static inline void apic_set_vector(int vec, void *bitmap)
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{
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set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
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}
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static inline void apic_clear_vector(int vec, void *bitmap)
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{
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clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
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@ -212,7 +198,7 @@ static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
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{
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bool enabled = val & APIC_SPIV_APIC_ENABLED;
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apic_set_reg(apic, APIC_SPIV, val);
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kvm_lapic_set_reg(apic, APIC_SPIV, val);
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if (enabled != apic->sw_enabled) {
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apic->sw_enabled = enabled;
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@ -226,13 +212,13 @@ static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
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static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
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{
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apic_set_reg(apic, APIC_ID, id << 24);
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kvm_lapic_set_reg(apic, APIC_ID, id << 24);
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recalculate_apic_map(apic->vcpu->kvm);
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}
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static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
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{
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apic_set_reg(apic, APIC_LDR, id);
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kvm_lapic_set_reg(apic, APIC_LDR, id);
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recalculate_apic_map(apic->vcpu->kvm);
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}
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@ -240,8 +226,8 @@ static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
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{
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u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
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apic_set_reg(apic, APIC_ID, id << 24);
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apic_set_reg(apic, APIC_LDR, ldr);
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kvm_lapic_set_reg(apic, APIC_ID, id << 24);
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kvm_lapic_set_reg(apic, APIC_LDR, ldr);
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recalculate_apic_map(apic->vcpu->kvm);
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}
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@ -287,10 +273,10 @@ void kvm_apic_set_version(struct kvm_vcpu *vcpu)
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feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
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if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
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v |= APIC_LVR_DIRECTED_EOI;
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apic_set_reg(apic, APIC_LVR, v);
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kvm_lapic_set_reg(apic, APIC_LVR, v);
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}
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static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
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static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
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LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
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LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
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LVT_MASK | APIC_MODE_MASK, /* LVTPC */
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@ -349,16 +335,6 @@ void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
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}
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EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
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static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
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{
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apic_set_vector(vec, apic->regs + APIC_IRR);
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/*
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* irr_pending must be true if any interrupt is pending; set it after
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* APIC_IRR to avoid race with apic_clear_irr
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*/
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apic->irr_pending = true;
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}
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static inline int apic_search_irr(struct kvm_lapic *apic)
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{
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return find_highest_vector(apic->regs + APIC_IRR);
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@ -563,7 +539,7 @@ static void apic_update_ppr(struct kvm_lapic *apic)
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apic, ppr, isr, isrv);
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if (old_ppr != ppr) {
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apic_set_reg(apic, APIC_PROCPRI, ppr);
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kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
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if (ppr < old_ppr)
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kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
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}
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@ -571,7 +547,7 @@ static void apic_update_ppr(struct kvm_lapic *apic)
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static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
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{
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apic_set_reg(apic, APIC_TASKPRI, tpr);
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kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
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apic_update_ppr(apic);
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}
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@ -668,6 +644,7 @@ bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
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return false;
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}
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}
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EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
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int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
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const unsigned long *bitmap, u32 bitmap_size)
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@ -921,7 +898,7 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
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if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
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if (trig_mode)
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apic_set_vector(vector, apic->regs + APIC_TMR);
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kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
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else
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apic_clear_vector(vector, apic->regs + APIC_TMR);
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}
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@ -929,7 +906,7 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
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if (vcpu->arch.apicv_active)
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kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
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else {
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apic_set_irr(vector, apic);
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kvm_lapic_set_irr(vector, apic);
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kvm_make_request(KVM_REQ_EVENT, vcpu);
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kvm_vcpu_kick(vcpu);
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@ -1186,7 +1163,7 @@ static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
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return container_of(dev, struct kvm_lapic, dev);
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}
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static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
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int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
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void *data)
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{
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unsigned char alignment = offset & 0xf;
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@ -1223,6 +1200,7 @@ static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
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static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
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{
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@ -1240,7 +1218,7 @@ static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
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if (!apic_mmio_in_range(apic, address))
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return -EOPNOTSUPP;
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apic_reg_read(apic, offset, len, data);
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kvm_lapic_reg_read(apic, offset, len, data);
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return 0;
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}
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@ -1425,7 +1403,7 @@ static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
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}
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}
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static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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{
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int ret = 0;
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@ -1457,7 +1435,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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case APIC_DFR:
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if (!apic_x2apic_mode(apic)) {
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apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
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kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
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recalculate_apic_map(apic->vcpu->kvm);
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} else
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ret = 1;
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@ -1472,10 +1450,10 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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int i;
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u32 lvt_val;
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for (i = 0; i < APIC_LVT_NUM; i++) {
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for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
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lvt_val = kvm_apic_get_reg(apic,
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APIC_LVTT + 0x10 * i);
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apic_set_reg(apic, APIC_LVTT + 0x10 * i,
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kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
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lvt_val | APIC_LVT_MASKED);
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}
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apic_update_lvtt(apic);
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@ -1486,14 +1464,14 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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}
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case APIC_ICR:
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/* No delay here, so we always clear the pending bit */
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apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
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kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
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apic_send_ipi(apic);
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break;
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case APIC_ICR2:
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if (!apic_x2apic_mode(apic))
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val &= 0xff000000;
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apic_set_reg(apic, APIC_ICR2, val);
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kvm_lapic_set_reg(apic, APIC_ICR2, val);
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break;
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case APIC_LVT0:
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@ -1507,7 +1485,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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val |= APIC_LVT_MASKED;
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val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
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apic_set_reg(apic, reg, val);
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kvm_lapic_set_reg(apic, reg, val);
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break;
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@ -1515,7 +1493,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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if (!kvm_apic_sw_enabled(apic))
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val |= APIC_LVT_MASKED;
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val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
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apic_set_reg(apic, APIC_LVTT, val);
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kvm_lapic_set_reg(apic, APIC_LVTT, val);
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apic_update_lvtt(apic);
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break;
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@ -1524,14 +1502,14 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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break;
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hrtimer_cancel(&apic->lapic_timer.timer);
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apic_set_reg(apic, APIC_TMICT, val);
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kvm_lapic_set_reg(apic, APIC_TMICT, val);
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start_apic_timer(apic);
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break;
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case APIC_TDCR:
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if (val & 4)
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apic_debug("KVM_WRITE:TDCR %x\n", val);
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apic_set_reg(apic, APIC_TDCR, val);
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kvm_lapic_set_reg(apic, APIC_TDCR, val);
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update_divide_count(apic);
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break;
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@ -1544,7 +1522,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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case APIC_SELF_IPI:
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if (apic_x2apic_mode(apic)) {
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apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
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kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
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} else
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ret = 1;
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break;
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@ -1556,6 +1534,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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apic_debug("Local APIC Write to read-only register %x\n", reg);
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return ret;
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}
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EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
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static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
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gpa_t address, int len, const void *data)
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@ -1585,14 +1564,14 @@ static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
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apic_debug("%s: offset 0x%x with length 0x%x, and value is "
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"0x%x\n", __func__, offset, len, val);
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apic_reg_write(apic, offset & 0xff0, val);
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kvm_lapic_reg_write(apic, offset & 0xff0, val);
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return 0;
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}
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void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
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{
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apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
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kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
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}
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EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
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@ -1604,10 +1583,10 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
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/* hw has done the conditional check and inst decode */
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offset &= 0xff0;
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apic_reg_read(vcpu->arch.apic, offset, 4, &val);
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kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
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/* TODO: optimize to just emulate side effect w/o one more write */
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apic_reg_write(vcpu->arch.apic, offset, val);
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kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
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}
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EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
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@ -1740,28 +1719,28 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
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kvm_apic_set_id(apic, vcpu->vcpu_id);
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kvm_apic_set_version(apic->vcpu);
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for (i = 0; i < APIC_LVT_NUM; i++)
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apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
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for (i = 0; i < KVM_APIC_LVT_NUM; i++)
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kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
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apic_update_lvtt(apic);
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if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
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apic_set_reg(apic, APIC_LVT0,
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kvm_lapic_set_reg(apic, APIC_LVT0,
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SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
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apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
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apic_set_reg(apic, APIC_DFR, 0xffffffffU);
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kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
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apic_set_spiv(apic, 0xff);
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apic_set_reg(apic, APIC_TASKPRI, 0);
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kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
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if (!apic_x2apic_mode(apic))
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kvm_apic_set_ldr(apic, 0);
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apic_set_reg(apic, APIC_ESR, 0);
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apic_set_reg(apic, APIC_ICR, 0);
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apic_set_reg(apic, APIC_ICR2, 0);
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apic_set_reg(apic, APIC_TDCR, 0);
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apic_set_reg(apic, APIC_TMICT, 0);
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kvm_lapic_set_reg(apic, APIC_ESR, 0);
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kvm_lapic_set_reg(apic, APIC_ICR, 0);
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kvm_lapic_set_reg(apic, APIC_ICR2, 0);
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kvm_lapic_set_reg(apic, APIC_TDCR, 0);
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kvm_lapic_set_reg(apic, APIC_TMICT, 0);
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for (i = 0; i < 8; i++) {
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apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
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apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
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apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
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kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
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kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
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kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
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}
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apic->irr_pending = vcpu->arch.apicv_active;
|
||||
apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
|
||||
|
|
@ -2139,8 +2118,8 @@ int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
|
|||
|
||||
/* if this is ICR write vector before command */
|
||||
if (reg == APIC_ICR)
|
||||
apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
|
||||
return apic_reg_write(apic, reg, (u32)data);
|
||||
kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
|
||||
return kvm_lapic_reg_write(apic, reg, (u32)data);
|
||||
}
|
||||
|
||||
int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
|
||||
|
|
@ -2157,10 +2136,10 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
|
|||
return 1;
|
||||
}
|
||||
|
||||
if (apic_reg_read(apic, reg, 4, &low))
|
||||
if (kvm_lapic_reg_read(apic, reg, 4, &low))
|
||||
return 1;
|
||||
if (reg == APIC_ICR)
|
||||
apic_reg_read(apic, APIC_ICR2, 4, &high);
|
||||
kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
|
||||
|
||||
*data = (((u64)high) << 32) | low;
|
||||
|
||||
|
|
@ -2176,8 +2155,8 @@ int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
|
|||
|
||||
/* if this is ICR write vector before command */
|
||||
if (reg == APIC_ICR)
|
||||
apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
|
||||
return apic_reg_write(apic, reg, (u32)data);
|
||||
kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
|
||||
return kvm_lapic_reg_write(apic, reg, (u32)data);
|
||||
}
|
||||
|
||||
int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
|
||||
|
|
@ -2188,10 +2167,10 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
|
|||
if (!lapic_in_kernel(vcpu))
|
||||
return 1;
|
||||
|
||||
if (apic_reg_read(apic, reg, 4, &low))
|
||||
if (kvm_lapic_reg_read(apic, reg, 4, &low))
|
||||
return 1;
|
||||
if (reg == APIC_ICR)
|
||||
apic_reg_read(apic, APIC_ICR2, 4, &high);
|
||||
kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
|
||||
|
||||
*data = (((u64)high) << 32) | low;
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
|
||||
#define KVM_APIC_INIT 0
|
||||
#define KVM_APIC_SIPI 1
|
||||
#define KVM_APIC_LVT_NUM 6
|
||||
|
||||
struct kvm_timer {
|
||||
struct hrtimer timer;
|
||||
|
|
@ -59,6 +60,11 @@ void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
|
|||
void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
|
||||
u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
|
||||
void kvm_apic_set_version(struct kvm_vcpu *vcpu);
|
||||
int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
|
||||
int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
|
||||
void *data);
|
||||
bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
|
||||
int short_hand, unsigned int dest, int dest_mode);
|
||||
|
||||
void __kvm_apic_update_irr(u32 *pir, void *regs);
|
||||
void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
|
||||
|
|
@ -99,11 +105,34 @@ static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
|
|||
int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
|
||||
void kvm_lapic_init(void);
|
||||
|
||||
#define VEC_POS(v) ((v) & (32 - 1))
|
||||
#define REG_POS(v) (((v) >> 5) << 4)
|
||||
|
||||
static inline void kvm_lapic_set_vector(int vec, void *bitmap)
|
||||
{
|
||||
set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
|
||||
}
|
||||
|
||||
static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
|
||||
{
|
||||
kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
|
||||
/*
|
||||
* irr_pending must be true if any interrupt is pending; set it after
|
||||
* APIC_IRR to avoid race with apic_clear_irr
|
||||
*/
|
||||
apic->irr_pending = true;
|
||||
}
|
||||
|
||||
static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off)
|
||||
{
|
||||
return *((u32 *) (apic->regs + reg_off));
|
||||
}
|
||||
|
||||
static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
|
||||
{
|
||||
*((u32 *) (apic->regs + reg_off)) = val;
|
||||
}
|
||||
|
||||
extern struct static_key kvm_no_apic_vcpu;
|
||||
|
||||
static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
|
||||
|
|
|
|||
Loading…
Reference in New Issue