iio: mma8452: Add highpass filter configuration.
Allow the cutoff frequency of the high pass filter to be configured. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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5dbbd19f11
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1e79841a00
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@ -29,9 +29,12 @@
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#define MMA8452_INT_SRC 0x0c
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#define MMA8452_WHO_AM_I 0x0d
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#define MMA8452_DATA_CFG 0x0e
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#define MMA8452_HP_FILTER_CUTOFF 0x0f
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#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK (BIT(0) | BIT(1))
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#define MMA8452_TRANSIENT_CFG 0x1d
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#define MMA8452_TRANSIENT_CFG_ELE BIT(4)
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#define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
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#define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
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#define MMA8452_TRANSIENT_SRC 0x1e
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#define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
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#define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
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@ -61,6 +64,7 @@
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#define MMA8452_DATA_CFG_FS_2G 0
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#define MMA8452_DATA_CFG_FS_4G 1
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#define MMA8452_DATA_CFG_FS_8G 2
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#define MMA8452_DATA_CFG_HPF_MASK BIT(4)
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#define MMA8452_INT_TRANS BIT(5)
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@ -158,6 +162,18 @@ static const int mma8452_transient_time_step_us[8] = {
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20000
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};
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/* Datasheet table 18 (normal mode) */
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static const int mma8452_hp_filter_cutoff[8][4][2] = {
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{ {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
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{ {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
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{ {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
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{ {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
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{ {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
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{ {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
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{ {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
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{ {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
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};
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static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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@ -172,9 +188,23 @@ static ssize_t mma8452_show_scale_avail(struct device *dev,
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ARRAY_SIZE(mma8452_scales));
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}
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static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct mma8452_data *data = iio_priv(indio_dev);
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int i = mma8452_get_odr_index(data);
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return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
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ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
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}
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static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
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static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
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mma8452_show_scale_avail, NULL, 0);
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static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
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S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
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static int mma8452_get_samp_freq_index(struct mma8452_data *data,
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int val, int val2)
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@ -190,6 +220,31 @@ static int mma8452_get_scale_index(struct mma8452_data *data,
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ARRAY_SIZE(mma8452_scales), val, val2);
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}
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static int mma8452_get_hp_filter_index(struct mma8452_data *data,
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int val, int val2)
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{
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int i = mma8452_get_odr_index(data);
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return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
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ARRAY_SIZE(mma8452_scales[0]), val, val2);
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}
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static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
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{
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int i, ret;
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ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
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if (ret < 0)
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return ret;
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i = mma8452_get_odr_index(data);
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ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
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*hz = mma8452_hp_filter_cutoff[i][ret][0];
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*uHz = mma8452_hp_filter_cutoff[i][ret][1];
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return 0;
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}
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static int mma8452_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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@ -228,6 +283,16 @@ static int mma8452_read_raw(struct iio_dev *indio_dev,
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return ret;
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*val = sign_extend32(ret, 7);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
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if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
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ret = mma8452_read_hp_filter(data, val, val2);
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if (ret < 0)
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return ret;
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} else {
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*val = 0;
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*val2 = 0;
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}
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return IIO_VAL_INT_PLUS_MICRO;
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}
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return -EINVAL;
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}
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@ -269,12 +334,31 @@ fail:
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return ret;
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}
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static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
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int val, int val2)
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{
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int i, reg;
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i = mma8452_get_hp_filter_index(data, val, val2);
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if (i < 0)
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return -EINVAL;
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reg = i2c_smbus_read_byte_data(data->client,
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MMA8452_HP_FILTER_CUTOFF);
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if (reg < 0)
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return reg;
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reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
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reg |= i;
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return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
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}
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static int mma8452_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct mma8452_data *data = iio_priv(indio_dev);
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int i;
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int i, ret;
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if (iio_buffer_enabled(indio_dev))
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return -EBUSY;
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@ -302,6 +386,19 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
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return -EINVAL;
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return mma8452_change_config(data, MMA8452_OFF_X +
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chan->scan_index, val);
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case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
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if (val == 0 && val2 == 0) {
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data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
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} else {
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data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
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ret = mma8452_set_hp_filter_frequency(data, val, val2);
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if (ret < 0)
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return ret;
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}
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return mma8452_change_config(data, MMA8452_DATA_CFG,
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data->data_cfg);
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default:
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return -EINVAL;
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}
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@ -339,6 +436,22 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev,
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*val2 = us % USEC_PER_SEC;
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return IIO_VAL_INT_PLUS_MICRO;
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case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
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ret = i2c_smbus_read_byte_data(data->client,
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MMA8452_TRANSIENT_CFG);
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if (ret < 0)
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return ret;
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if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
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*val = 0;
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*val2 = 0;
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} else {
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ret = mma8452_read_hp_filter(data, val, val2);
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if (ret < 0)
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return ret;
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}
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return IIO_VAL_INT_PLUS_MICRO;
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default:
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return -EINVAL;
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}
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@ -352,7 +465,7 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev,
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int val, int val2)
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{
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struct mma8452_data *data = iio_priv(indio_dev);
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int steps;
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int ret, reg, steps;
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switch (info) {
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case IIO_EV_INFO_VALUE:
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@ -369,6 +482,22 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev,
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return mma8452_change_config(data, MMA8452_TRANSIENT_COUNT,
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steps);
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case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
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reg = i2c_smbus_read_byte_data(data->client,
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MMA8452_TRANSIENT_CFG);
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if (reg < 0)
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return reg;
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if (val == 0 && val2 == 0) {
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reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
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} else {
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reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
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ret = mma8452_set_hp_filter_frequency(data, val, val2);
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if (ret < 0)
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return ret;
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}
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return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
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default:
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return -EINVAL;
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}
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@ -510,7 +639,8 @@ static const struct iio_event_spec mma8452_transient_event[] = {
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.dir = IIO_EV_DIR_RISING,
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.mask_separate = BIT(IIO_EV_INFO_ENABLE),
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.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
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BIT(IIO_EV_INFO_PERIOD)
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BIT(IIO_EV_INFO_PERIOD) |
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BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
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},
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};
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@ -537,7 +667,8 @@ static struct attribute_group mma8452_event_attribute_group = {
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_CALIBBIAS), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
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BIT(IIO_CHAN_INFO_SCALE), \
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BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
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.scan_index = idx, \
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.scan_type = { \
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.sign = 's', \
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@ -560,6 +691,7 @@ static const struct iio_chan_spec mma8452_channels[] = {
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static struct attribute *mma8452_attributes[] = {
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&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
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&iio_dev_attr_in_accel_scale_available.dev_attr.attr,
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&iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
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NULL
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};
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