ARM: dts: dra7: fix cpsw mdio fck clock
commit5.4-rM2-2.2.x-imx-squashed6af0a549c2
upstream. The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0) is specified incorrectly, which is caused incorrect MDIO bus clock configuration MDCLK. The correct CPSW MDIO functional clock is gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it. Fixes:1faa415c9c
("ARM: dts: Add fck for cpsw mdio for omap variants") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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51cca512d0
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1ee117bbce
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@ -3059,7 +3059,7 @@
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davinci_mdio: mdio@1000 {
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compatible = "ti,cpsw-mdio","ti,davinci_mdio";
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clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
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clocks = <&gmac_main_clk>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <0>;
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