ARM: SAMSUNG: Move GPIO common functions to plat-samsung
This patch moves GPIO common functions (from plat-s3c64xx) into plat-samsung. and adds the config option to build the plat-samsung/gpiolib for Samsung SoCs. Signed-off-by: Adityapratap Sharma <aditya.ps@samsung.com> Signed-off-by: Atul Dahiya <atul.dahiya@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Kukjin Kim
Ben Dooks
parent
9717453c40
commit
1f323cfda5
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@ -11,6 +11,11 @@
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* published by the Free Software Foundation.
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*/
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#define GPIOCON_OFF (0x00)
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#define GPIODAT_OFF (0x04)
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#define con_4bit_shift(__off) ((__off) * 4)
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/* Define the core gpiolib support functions that the s3c platforms may
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* need to extend or change depending on the hardware and the s3c chip
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* selected at build or found at run time.
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@ -80,6 +85,29 @@ extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
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* and any other necessary functions.
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*/
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/**
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* samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
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* @chip: The gpio chip that is being configured.
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* @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
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*
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* This helper deal with the GPIO cases where the control register has 4 bits
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* of control per GPIO, generally in the form of:
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* 0000 = Input
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* 0001 = Output
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* others = Special functions (dependant on bank)
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*
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* Note, since the code to deal with the case where there are two control
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* registers instead of one, we do not have a seperate set of function
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* (samsung_gpiolib_add_4bit2_chips)for each case.
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*/
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extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
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int nr_chips);
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extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
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int nr_chips);
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extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
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extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
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#ifdef CONFIG_S3C_GPIO_TRACK
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extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
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@ -22,6 +22,7 @@ config PLAT_S3C64XX
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select S3C_GPIO_CFG_S3C64XX
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select S3C_DEV_NAND
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select USB_ARCH_HAS_OHCI
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select SAMSUNG_GPIOLIB_4BIT
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help
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Base platform code for any Samsung S3C64XX device
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@ -49,150 +49,6 @@
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* [2] BANK has two control registers, GPxCON0 and GPxCON1
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*/
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#define OFF_GPCON (0x00)
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#define OFF_GPDAT (0x04)
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#define con_4bit_shift(__off) ((__off) * 4)
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#if 1
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#define gpio_dbg(x...) do { } while(0)
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#else
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#define gpio_dbg(x...) printk(KERN_DEBUG x)
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#endif
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/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
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* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
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* following example:
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*
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* base + 0x00: Control register, 4 bits per gpio
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x04: Data register, 1 bit per gpio
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* bit n: data bit n
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*
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* Note, since the data register is one bit per gpio and is at base + 0x4
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* we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
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* the output.
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*/
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static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long con;
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con = __raw_readl(base + OFF_GPCON);
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con &= ~(0xf << con_4bit_shift(offset));
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__raw_writel(con, base + OFF_GPCON);
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gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
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return 0;
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}
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static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long con;
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unsigned long dat;
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con = __raw_readl(base + OFF_GPCON);
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con &= ~(0xf << con_4bit_shift(offset));
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con |= 0x1 << con_4bit_shift(offset);
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dat = __raw_readl(base + OFF_GPDAT);
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if (value)
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dat |= 1 << offset;
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else
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dat &= ~(1 << offset);
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__raw_writel(dat, base + OFF_GPDAT);
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__raw_writel(con, base + OFF_GPCON);
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__raw_writel(dat, base + OFF_GPDAT);
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gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
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return 0;
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}
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/* The next set of routines are for the case where the GPIO configuration
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* registers are 4 bits per GPIO but there is more than one register (the
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* bank has more than 8 GPIOs.
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*
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* This case is the similar to the 4 bit case, but the registers are as
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* follows:
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*
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* base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x08: Data register, 1 bit per gpio
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* bit n: data bit n
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*
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* To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
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* store the 'base + 0x4' address so that these routines see the data
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* register at ourchip->base + 0x04.
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*/
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static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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void __iomem *regcon = base;
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unsigned long con;
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if (offset > 7)
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offset -= 8;
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else
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regcon -= 4;
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con = __raw_readl(regcon);
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con &= ~(0xf << con_4bit_shift(offset));
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__raw_writel(con, regcon);
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gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
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return 0;
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}
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static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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void __iomem *regcon = base;
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unsigned long con;
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unsigned long dat;
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if (offset > 7)
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offset -= 8;
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else
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regcon -= 4;
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con = __raw_readl(regcon);
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con &= ~(0xf << con_4bit_shift(offset));
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con |= 0x1 << con_4bit_shift(offset);
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dat = __raw_readl(base + OFF_GPDAT);
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if (value)
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dat |= 1 << offset;
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else
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dat &= ~(1 << offset);
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__raw_writel(dat, base + OFF_GPDAT);
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__raw_writel(con, regcon);
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__raw_writel(dat, base + OFF_GPDAT);
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gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
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return 0;
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}
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static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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@ -399,20 +255,6 @@ static struct s3c_gpio_chip gpio_2bit[] = {
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},
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};
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static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
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{
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chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
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chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
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chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
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}
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static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
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{
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chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
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chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
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chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
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}
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static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
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{
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chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
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@ -432,10 +274,10 @@ static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
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static __init int s3c64xx_gpiolib_init(void)
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{
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s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
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s3c64xx_gpiolib_add_4bit);
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samsung_gpiolib_add_4bit);
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s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
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s3c64xx_gpiolib_add_4bit2);
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samsung_gpiolib_add_4bit2);
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s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
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s3c64xx_gpiolib_add_2bit);
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@ -33,6 +33,13 @@ config SAMSUNG_IRQ_UART
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# options for gpio configuration support
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config SAMSUNG_GPIOLIB_4BIT
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bool
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help
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GPIOlib file contains the 4 bit modification functions for gpio
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configuration. GPIOlib shall be compiled only for S3C64XX and S5P
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series of processors.
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config S3C_GPIO_CFG_S3C24XX
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bool
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help
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@ -15,6 +15,7 @@ obj-y += clock.o
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obj-y += pwm-clock.o
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obj-y += gpio-config.o
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obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT) += gpiolib.o
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obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
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obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o
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197
arch/arm/plat-samsung/gpiolib.c
Normal file
197
arch/arm/plat-samsung/gpiolib.c
Normal file
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@ -0,0 +1,197 @@
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/* arch/arm/plat-samsung/gpiolib.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* SAMSUNG - GPIOlib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/gpio.h>
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#include <plat/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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#ifndef DEBUG_GPIO
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#define gpio_dbg(x...) do { } while (0)
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#else
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#define gpio_dbg(x...) printk(KERN_DEBUG x)
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#endif
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/* The samsung_gpiolib_4bit routines are to control the gpio banks where
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* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
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* following example:
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*
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* base + 0x00: Control register, 4 bits per gpio
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x04: Data register, 1 bit per gpio
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* bit n: data bit n
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*
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* Note, since the data register is one bit per gpio and is at base + 0x4
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* we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
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* the output.
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*/
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int samsung_gpiolib_4bit_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long con;
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con = __raw_readl(base + GPIOCON_OFF);
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con &= ~(0xf << con_4bit_shift(offset));
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__raw_writel(con, base + GPIOCON_OFF);
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gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
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return 0;
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}
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int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long con;
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unsigned long dat;
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con = __raw_readl(base + GPIOCON_OFF);
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con &= ~(0xf << con_4bit_shift(offset));
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con |= 0x1 << con_4bit_shift(offset);
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dat = __raw_readl(base + GPIODAT_OFF);
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if (value)
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dat |= 1 << offset;
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else
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dat &= ~(1 << offset);
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__raw_writel(dat, base + GPIODAT_OFF);
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__raw_writel(con, base + GPIOCON_OFF);
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__raw_writel(dat, base + GPIODAT_OFF);
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gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
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return 0;
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}
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/* The next set of routines are for the case where the GPIO configuration
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* registers are 4 bits per GPIO but there is more than one register (the
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* bank has more than 8 GPIOs.
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*
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* This case is the similar to the 4 bit case, but the registers are as
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* follows:
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*
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* base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x08: Data register, 1 bit per gpio
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* bit n: data bit n
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*
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* To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
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* store the 'base + 0x4' address so that these routines see the data
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* register at ourchip->base + 0x04.
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*/
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int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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void __iomem *regcon = base;
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unsigned long con;
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if (offset > 7)
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offset -= 8;
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else
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regcon -= 4;
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con = __raw_readl(regcon);
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con &= ~(0xf << con_4bit_shift(offset));
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__raw_writel(con, regcon);
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gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
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return 0;
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}
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int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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void __iomem *regcon = base;
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unsigned long con;
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unsigned long dat;
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unsigned con_offset = offset;
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if (con_offset > 7)
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con_offset -= 8;
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else
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regcon -= 4;
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con = __raw_readl(regcon);
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con &= ~(0xf << con_4bit_shift(con_offset));
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con |= 0x1 << con_4bit_shift(con_offset);
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dat = __raw_readl(base + GPIODAT_OFF);
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if (value)
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dat |= 1 << offset;
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else
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dat &= ~(1 << offset);
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__raw_writel(dat, base + GPIODAT_OFF);
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__raw_writel(con, regcon);
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__raw_writel(dat, base + GPIODAT_OFF);
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gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
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return 0;
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}
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|
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void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
chip->chip.direction_input = samsung_gpiolib_4bit_input;
|
||||
chip->chip.direction_output = samsung_gpiolib_4bit_output;
|
||||
chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
|
||||
}
|
||||
|
||||
void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
chip->chip.direction_input = samsung_gpiolib_4bit2_input;
|
||||
chip->chip.direction_output = samsung_gpiolib_4bit2_output;
|
||||
chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
|
||||
}
|
||||
|
||||
void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
|
||||
int nr_chips)
|
||||
{
|
||||
for (; nr_chips > 0; nr_chips--, chip++) {
|
||||
samsung_gpiolib_add_4bit(chip);
|
||||
s3c_gpiolib_add(chip);
|
||||
}
|
||||
}
|
||||
|
||||
void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
|
||||
int nr_chips)
|
||||
{
|
||||
for (; nr_chips > 0; nr_chips--, chip++) {
|
||||
samsung_gpiolib_add_4bit2(chip);
|
||||
s3c_gpiolib_add(chip);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue