Staging: ipack/devices/ipoctal: Tidy up ipoctal some more.
No need to have a struct when it has only one field. Signed-off-by: Jens Taprogge <jens.taprogge@taprogge.org> Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jens Taprogge
Greg Kroah-Hartman
parent
a498899a3e
commit
1f43d7bfac
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@ -40,8 +40,8 @@ struct ipoctal {
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struct list_head list;
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struct ipack_device *dev;
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unsigned int board_id;
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struct scc2698_channel __iomem *chan_regs;
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struct scc2698_block __iomem *block_regs;
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union scc2698_channel __iomem *chan_regs;
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union scc2698_block __iomem *block_regs;
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struct ipoctal_stats chan_stats[NR_CHANNELS];
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unsigned int nb_bytes[NR_CHANNELS];
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unsigned int count_wr[NR_CHANNELS];
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@ -103,7 +103,7 @@ static int ipoctal_port_activate(struct tty_port *port, struct tty_struct *tty)
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return -ENODEV;
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}
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_ENABLE_RX);
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return 0;
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}
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@ -216,9 +216,9 @@ static int ipoctal_irq_handler(void *arg)
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*/
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block = channel / 2;
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isr = ipoctal_read_io_reg(ipoctal,
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&ipoctal->block_regs[block].u.r.isr);
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&ipoctal->block_regs[block].r.isr);
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sr = ipoctal_read_io_reg(ipoctal,
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&ipoctal->chan_regs[channel].u.r.sr);
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&ipoctal->chan_regs[channel].r.sr);
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if ((channel % 2) == 1) {
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isr_tx_rdy = isr & ISR_TxRDY_B;
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@ -235,13 +235,13 @@ static int ipoctal_irq_handler(void *arg)
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(sr & SR_TX_EMPTY) &&
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(ipoctal->nb_bytes[channel] == 0)) {
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->chan_regs[channel].u.w.cr,
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&ipoctal->chan_regs[channel].w.cr,
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CR_DISABLE_TX);
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ipoctal_write_cr_cmd(ipoctal,
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&ipoctal->chan_regs[channel].u.w.cr,
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&ipoctal->chan_regs[channel].w.cr,
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CR_CMD_NEGATE_RTSN);
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->chan_regs[channel].u.w.cr,
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&ipoctal->chan_regs[channel].w.cr,
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CR_ENABLE_RX);
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ipoctal->write = 1;
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wake_up_interruptible(&ipoctal->queue[channel]);
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@ -250,13 +250,13 @@ static int ipoctal_irq_handler(void *arg)
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/* RX data */
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if (isr_rx_rdy && (sr & SR_RX_READY)) {
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value = ipoctal_read_io_reg(ipoctal,
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&ipoctal->chan_regs[channel].u.r.rhr);
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&ipoctal->chan_regs[channel].r.rhr);
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flag = TTY_NORMAL;
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/* Error: count statistics */
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if (sr & SR_ERROR) {
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ipoctal_write_cr_cmd(ipoctal,
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&ipoctal->chan_regs[channel].u.w.cr,
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&ipoctal->chan_regs[channel].w.cr,
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CR_CMD_RESET_ERR_STATUS);
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if (sr & SR_OVERRUN_ERROR) {
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@ -293,7 +293,7 @@ static int ipoctal_irq_handler(void *arg)
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value = ipoctal->tty_port[channel].xmit_buf[*pointer_write];
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->chan_regs[channel].u.w.thr,
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&ipoctal->chan_regs[channel].w.thr,
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value);
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ipoctal->chan_stats[channel].tx++;
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ipoctal->count_wr[channel]++;
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@ -391,40 +391,40 @@ static int ipoctal_inst_slot(struct ipoctal *ipoctal, unsigned int bus_nr,
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/* Save the virtual address to access the registers easily */
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ipoctal->chan_regs =
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(struct scc2698_channel __iomem *) ipoctal->dev->io_space.address;
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(union scc2698_channel __iomem *) ipoctal->dev->io_space.address;
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ipoctal->block_regs =
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(struct scc2698_block __iomem *) ipoctal->dev->io_space.address;
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(union scc2698_block __iomem *) ipoctal->dev->io_space.address;
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/* Disable RX and TX before touching anything */
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for (i = 0; i < NR_CHANNELS ; i++) {
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[i].u.w.cr,
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[i].w.cr,
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CR_DISABLE_RX | CR_DISABLE_TX);
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[i].u.w.cr,
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[i].w.cr,
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CR_CMD_RESET_RX);
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[i].u.w.cr,
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[i].w.cr,
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CR_CMD_RESET_TX);
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->chan_regs[i].u.w.mr,
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&ipoctal->chan_regs[i].w.mr,
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MR1_CHRL_8_BITS | MR1_ERROR_CHAR |
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MR1_RxINT_RxRDY); /* mr1 */
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->chan_regs[i].u.w.mr,
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&ipoctal->chan_regs[i].w.mr,
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0); /* mr2 */
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->chan_regs[i].u.w.csr,
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&ipoctal->chan_regs[i].w.csr,
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TX_CLK_9600 | RX_CLK_9600);
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}
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for (i = 0; i < IP_OCTAL_NB_BLOCKS; i++) {
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->block_regs[i].u.w.acr,
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&ipoctal->block_regs[i].w.acr,
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ACR_BRG_SET2);
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->block_regs[i].u.w.opcr,
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&ipoctal->block_regs[i].w.opcr,
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OPCR_MPP_OUTPUT | OPCR_MPOa_RTSN |
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OPCR_MPOb_RTSN);
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->block_regs[i].u.w.imr,
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&ipoctal->block_regs[i].w.imr,
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IMR_TxRDY_A | IMR_RxRDY_FFULL_A |
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IMR_DELTA_BREAK_A | IMR_TxRDY_B |
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IMR_RxRDY_FFULL_B | IMR_DELTA_BREAK_B);
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@ -495,7 +495,7 @@ static int ipoctal_inst_slot(struct ipoctal *ipoctal, unsigned int bus_nr,
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* Enable again the RX. TX will be enabled when
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* there is something to send
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*/
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[i].u.w.cr,
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[i].w.cr,
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CR_ENABLE_RX);
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}
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@ -545,10 +545,10 @@ static int ipoctal_write(struct ipoctal *ipoctal, unsigned int channel,
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/* As the IP-OCTAL 485 only supports half duplex, do it manually */
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if (ipoctal->board_id == IP_OCTAL_485_ID) {
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->chan_regs[channel].u.w.cr,
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&ipoctal->chan_regs[channel].w.cr,
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CR_DISABLE_RX);
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ipoctal_write_cr_cmd(ipoctal,
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&ipoctal->chan_regs[channel].u.w.cr,
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&ipoctal->chan_regs[channel].w.cr,
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CR_CMD_ASSERT_RTSN);
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}
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@ -557,11 +557,11 @@ static int ipoctal_write(struct ipoctal *ipoctal, unsigned int channel,
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* operations
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*/
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->chan_regs[channel].u.w.cr,
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&ipoctal->chan_regs[channel].w.cr,
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CR_ENABLE_TX);
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wait_event_interruptible(ipoctal->queue[channel], ipoctal->write);
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ipoctal_write_io_reg(ipoctal,
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&ipoctal->chan_regs[channel].u.w.cr,
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&ipoctal->chan_regs[channel].w.cr,
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CR_DISABLE_TX);
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ipoctal->write = 0;
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@ -607,15 +607,15 @@ static void ipoctal_set_termios(struct tty_struct *tty,
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cflag = tty->termios->c_cflag;
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/* Disable and reset everything before change the setup */
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_DISABLE_RX | CR_DISABLE_TX);
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_CMD_RESET_RX);
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_CMD_RESET_TX);
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_CMD_RESET_ERR_STATUS);
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_CMD_RESET_MR);
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/* Set Bits per chars */
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@ -729,12 +729,12 @@ static void ipoctal_set_termios(struct tty_struct *tty,
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mr1 |= MR1_RxINT_RxRDY;
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/* Write the control registers */
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].u.w.mr, mr1);
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].u.w.mr, mr2);
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].u.w.csr, csr);
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].w.mr, mr1);
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].w.mr, mr2);
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].w.csr, csr);
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/* Enable again the RX */
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_ENABLE_RX);
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}
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@ -755,15 +755,15 @@ static void ipoctal_hangup(struct tty_struct *tty)
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tty_port_hangup(&ipoctal->tty_port[channel]);
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_io_reg(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_DISABLE_RX | CR_DISABLE_TX);
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_CMD_RESET_RX);
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_CMD_RESET_TX);
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_CMD_RESET_ERR_STATUS);
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].u.w.cr,
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ipoctal_write_cr_cmd(ipoctal, &ipoctal->chan_regs[channel].w.cr,
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CR_CMD_RESET_MR);
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clear_bit(ASYNCB_INITIALIZED, &ipoctal->tty_port[channel].flags);
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@ -15,78 +15,74 @@
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#define SCC2698_H_
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/*
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* struct scc2698_channel - Channel access to scc2698 IO
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* union scc2698_channel - Channel access to scc2698 IO
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*
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* dn value are only spacer.
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*
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*/
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struct scc2698_channel {
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union {
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struct {
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u8 d0, mr; /* Mode register 1/2*/
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u8 d1, sr; /* Status register */
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u8 d2, r1; /* reserved */
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u8 d3, rhr; /* Receive holding register (R) */
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u8 junk[8]; /* other crap for block control */
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} __packed r; /* Read access */
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struct {
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u8 d0, mr; /* Mode register 1/2 */
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u8 d1, csr; /* Clock select register */
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u8 d2, cr; /* Command register */
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u8 d3, thr; /* Transmit holding register */
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u8 junk[8]; /* other crap for block control */
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} __packed w; /* Write access */
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} u;
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} __packed;
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union scc2698_channel {
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struct {
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u8 d0, mr; /* Mode register 1/2*/
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u8 d1, sr; /* Status register */
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u8 d2, r1; /* reserved */
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u8 d3, rhr; /* Receive holding register (R) */
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u8 junk[8]; /* other crap for block control */
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} __packed r; /* Read access */
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struct {
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u8 d0, mr; /* Mode register 1/2 */
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u8 d1, csr; /* Clock select register */
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u8 d2, cr; /* Command register */
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u8 d3, thr; /* Transmit holding register */
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u8 junk[8]; /* other crap for block control */
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} __packed w; /* Write access */
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};
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/*
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* struct scc2698_block - Block access to scc2698 IO
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* union scc2698_block - Block access to scc2698 IO
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*
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* The scc2698 contain 4 block.
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* Each block containt two channel a and b.
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* dn value are only spacer.
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*
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*/
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struct scc2698_block {
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union {
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struct {
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u8 d0, mra; /* Mode register 1/2 (a) */
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u8 d1, sra; /* Status register (a) */
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u8 d2, r1; /* reserved */
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u8 d3, rhra; /* Receive holding register (a) */
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u8 d4, ipcr; /* Input port change register of block */
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u8 d5, isr; /* Interrupt status register of block */
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u8 d6, ctur; /* Counter timer upper register of block */
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u8 d7, ctlr; /* Counter timer lower register of block */
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u8 d8, mrb; /* Mode register 1/2 (b) */
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u8 d9, srb; /* Status register (b) */
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u8 da, r2; /* reserved */
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u8 db, rhrb; /* Receive holding register (b) */
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u8 dc, r3; /* reserved */
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u8 dd, ip; /* Input port register of block */
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u8 de, ctg; /* Start counter timer of block */
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u8 df, cts; /* Stop counter timer of block */
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} __packed r; /* Read access */
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struct {
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u8 d0, mra; /* Mode register 1/2 (a) */
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u8 d1, csra; /* Clock select register (a) */
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u8 d2, cra; /* Command register (a) */
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u8 d3, thra; /* Transmit holding register (a) */
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u8 d4, acr; /* Auxiliary control register of block */
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u8 d5, imr; /* Interrupt mask register of block */
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u8 d6, ctu; /* Counter timer upper register of block */
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u8 d7, ctl; /* Counter timer lower register of block */
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u8 d8, mrb; /* Mode register 1/2 (b) */
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u8 d9, csrb; /* Clock select register (a) */
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u8 da, crb; /* Command register (b) */
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u8 db, thrb; /* Transmit holding register (b) */
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u8 dc, r1; /* reserved */
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u8 dd, opcr; /* Output port configuration register of block */
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u8 de, r2; /* reserved */
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u8 df, r3; /* reserved */
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} __packed w; /* Write access */
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} u;
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} __packed;
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union scc2698_block {
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struct {
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u8 d0, mra; /* Mode register 1/2 (a) */
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u8 d1, sra; /* Status register (a) */
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u8 d2, r1; /* reserved */
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u8 d3, rhra; /* Receive holding register (a) */
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u8 d4, ipcr; /* Input port change register of block */
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u8 d5, isr; /* Interrupt status register of block */
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u8 d6, ctur; /* Counter timer upper register of block */
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u8 d7, ctlr; /* Counter timer lower register of block */
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u8 d8, mrb; /* Mode register 1/2 (b) */
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u8 d9, srb; /* Status register (b) */
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u8 da, r2; /* reserved */
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u8 db, rhrb; /* Receive holding register (b) */
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u8 dc, r3; /* reserved */
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u8 dd, ip; /* Input port register of block */
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u8 de, ctg; /* Start counter timer of block */
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u8 df, cts; /* Stop counter timer of block */
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} __packed r; /* Read access */
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struct {
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u8 d0, mra; /* Mode register 1/2 (a) */
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u8 d1, csra; /* Clock select register (a) */
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u8 d2, cra; /* Command register (a) */
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u8 d3, thra; /* Transmit holding register (a) */
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u8 d4, acr; /* Auxiliary control register of block */
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u8 d5, imr; /* Interrupt mask register of block */
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u8 d6, ctu; /* Counter timer upper register of block */
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u8 d7, ctl; /* Counter timer lower register of block */
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u8 d8, mrb; /* Mode register 1/2 (b) */
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u8 d9, csrb; /* Clock select register (a) */
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u8 da, crb; /* Command register (b) */
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u8 db, thrb; /* Transmit holding register (b) */
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u8 dc, r1; /* reserved */
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u8 dd, opcr; /* Output port configuration register of block */
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u8 de, r2; /* reserved */
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u8 df, r3; /* reserved */
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} __packed w; /* Write access */
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};
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#define MR1_CHRL_5_BITS (0x0 << 0)
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#define MR1_CHRL_6_BITS (0x1 << 0)
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|
|
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Loading…
Reference in a new issue