Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (21 commits) sh: fix sh2a cache entry_mask sh: Enable NFS root in Migo-R defconfig. sh: FTRACE renamed to FUNCTION_TRACER. sh: Fix up the shared IRQ demuxer's control bit testing logic. Define SCSPTR1 for SH 7751R sh: Add sci_rxd_in of SH4-202 Add support usb setting on sh 7366 sh: Change register name SCSPTR to SCSPTR2 sh: use the new byteorder headers. sh: SHmedia ISA tuning fixups. sh: Kill off long-dead HD64465 cchip support. sh: Revert "SH 7366 needs SCIF_ONLY" sh: Simplify and lock down the ISA tuning. sh: sh7785lcr: Select uImage as default image target. sh: Add on-chip RTC support for SH7722. SH 7366 needs SCIF_ONLY gdrom: Fix compile error sh: Provide a sample defconfig for the UL2 (SH7366) board. sh: Fix FPU tuning on toolchains with mismatched multilib targets. sh: oprofile: Fix up the SH7750 performance counter name. ...
This commit is contained in:
commit
1fe01cb57c
|
@ -47,9 +47,7 @@ Next, for companion chips:
|
|||
`-- sh
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`-- cchips
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||||
`-- hd6446x
|
||||
|-- hd64461
|
||||
| `-- cchip-specific files
|
||||
`-- hd64465
|
||||
`-- hd64461
|
||||
`-- cchip-specific files
|
||||
|
||||
... and so on. Headers for the companion chips are treated the same way as
|
||||
|
|
|
@ -24,7 +24,7 @@ config SUPERH32
|
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select HAVE_KPROBES
|
||||
select HAVE_KRETPROBES
|
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select HAVE_ARCH_TRACEHOOK
|
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select HAVE_FTRACE
|
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select HAVE_FUNCTION_TRACER
|
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|
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config SUPERH64
|
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def_bool y if CPU_SH5
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|
|
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@ -2,7 +2,7 @@
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# arch/sh/Makefile
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#
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# Copyright (C) 1999 Kaz Kojima
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# Copyright (C) 2002, 2003, 2004 Paul Mundt
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# Copyright (C) 2002 - 2008 Paul Mundt
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# Copyright (C) 2002 M. R. Brown
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#
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# This file is subject to the terms and conditions of the GNU General Public
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|
@ -18,15 +18,11 @@ isa-$(CONFIG_CPU_SH4) := sh4
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isa-$(CONFIG_CPU_SH4A) := sh4a
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isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al
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isa-$(CONFIG_CPU_SH5) := shmedia
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ifeq ($(CONFIG_SUPERH32),y)
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isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp
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ifndef CONFIG_SH_DSP
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ifndef CONFIG_SH_FPU
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isa-y := $(isa-y)-nofpu
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isa-y := $(isa-y)-up
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endif
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endif
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isa-y := $(isa-y)-up
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cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,)
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cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \
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|
@ -38,6 +34,22 @@ cflags-$(CONFIG_CPU_SH4A) += $(call cc-option,-m4a,) \
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$(call cc-option,-m4a-nofpu,)
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cflags-$(CONFIG_CPU_SH5) := $(call cc-option,-m5-32media-nofpu,)
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ifeq ($(cflags-y),)
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#
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# In the case where we are stuck with a compiler that has been uselessly
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# restricted to a particular ISA, a favourite default of newer GCCs when
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# extensive multilib targets are not provided, ensure we get the best fit
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# regarding FP generation. This is necessary to avoid references to FP
|
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# variants in libgcc where integer variants exist, which otherwise result
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# in link errors. This is intentionally stupid (albeit many orders of
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# magnitude less than GCC's default behaviour), as anything with a large
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# number of multilib targets better have been built correctly for
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# the target in mind.
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#
|
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cflags-y += $(shell $(CC) $(KBUILD_CFLAGS) -print-multi-lib | \
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grep nofpu | sed q | sed -e 's/^/-/;s/;.*$$//')
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endif
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|
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cflags-$(CONFIG_CPU_BIG_ENDIAN) += -mb
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cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -ml
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|
||||
|
@ -65,7 +77,8 @@ OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \
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-R .stab -R .stabstr -S
|
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|
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# Give the various platforms the opportunity to set default image types
|
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defaultimage-$(CONFIG_SUPERH32) := zImage
|
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defaultimage-$(CONFIG_SUPERH32) := zImage
|
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defaultimage-$(CONFIG_SH_SH7785LCR) := uImage
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|
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# Set some sensible Kbuild defaults
|
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KBUILD_DEFCONFIG := shx3_defconfig
|
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|
|
|
@ -23,7 +23,7 @@ IMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \
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|||
|
||||
LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
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|
||||
ifeq ($(CONFIG_FTRACE),y)
|
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ifeq ($(CONFIG_FUNCTION_TRACER),y)
|
||||
ORIG_CFLAGS := $(KBUILD_CFLAGS)
|
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KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
|
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endif
|
||||
|
|
|
@ -22,20 +22,6 @@ config HD64461
|
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Say Y if you want support for the HD64461.
|
||||
Otherwise, say N.
|
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|
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config HD64465
|
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bool "Hitachi HD64465 companion chip support"
|
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---help---
|
||||
The Hitachi HD64465 provides an interface for
|
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the SH7750 CPU, supporting a LCD controller,
|
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CRT color controller, IrDA, USB, PCMCIA,
|
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keyboard controller, and a printer interface.
|
||||
|
||||
More information is available at
|
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<http://global.hitachi.com/New/cnews/E/1998/981019B.html>.
|
||||
|
||||
Say Y if you want support for the HD64465.
|
||||
Otherwise, say N.
|
||||
|
||||
endchoice
|
||||
|
||||
# These will also be split into the Kconfig's below
|
||||
|
@ -61,23 +47,4 @@ config HD64461_ENABLER
|
|||
via the HD64461 companion chip.
|
||||
Otherwise, say N.
|
||||
|
||||
config HD64465_IOBASE
|
||||
hex "HD64465 start address"
|
||||
depends on HD64465
|
||||
default "0xb0000000"
|
||||
help
|
||||
The default setting of the HD64465 IO base address is 0xb0000000.
|
||||
|
||||
Do not change this unless you know what you are doing.
|
||||
|
||||
config HD64465_IRQ
|
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int "HD64465 IRQ"
|
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depends on HD64465
|
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default "5"
|
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help
|
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The default setting of the HD64465 IRQ is 5.
|
||||
|
||||
Do not change this unless you know what you are doing.
|
||||
|
||||
endmenu
|
||||
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
obj-$(CONFIG_HD64461) += hd64461.o
|
||||
obj-$(CONFIG_HD64465) += hd64465/
|
||||
|
||||
EXTRA_CFLAGS += -Werror
|
||||
|
|
|
@ -1,6 +0,0 @@
|
|||
#
|
||||
# Makefile for the HD64465
|
||||
#
|
||||
|
||||
obj-y := setup.o io.o gpio.o
|
||||
|
|
@ -1,196 +0,0 @@
|
|||
/*
|
||||
* $Id: gpio.c,v 1.4 2003/05/19 22:24:18 lethal Exp $
|
||||
* by Greg Banks <gbanks@pocketpenguins.com>
|
||||
* (c) 2000 PocketPenguins Inc
|
||||
*
|
||||
* GPIO pin support for HD64465 companion chip.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/hd64465/gpio.h>
|
||||
|
||||
#define _PORTOF(portpin) (((portpin)>>3)&0x7)
|
||||
#define _PINOF(portpin) ((portpin)&0x7)
|
||||
|
||||
/* Register addresses parametrised on port */
|
||||
#define GPIO_CR(port) (HD64465_REG_GPACR+((port)<<1))
|
||||
#define GPIO_DR(port) (HD64465_REG_GPADR+((port)<<1))
|
||||
#define GPIO_ICR(port) (HD64465_REG_GPAICR+((port)<<1))
|
||||
#define GPIO_ISR(port) (HD64465_REG_GPAISR+((port)<<1))
|
||||
|
||||
#define GPIO_NPORTS 5
|
||||
|
||||
#define MODNAME "hd64465_gpio"
|
||||
|
||||
EXPORT_SYMBOL(hd64465_gpio_configure);
|
||||
EXPORT_SYMBOL(hd64465_gpio_get_pin);
|
||||
EXPORT_SYMBOL(hd64465_gpio_get_port);
|
||||
EXPORT_SYMBOL(hd64465_gpio_register_irq);
|
||||
EXPORT_SYMBOL(hd64465_gpio_set_pin);
|
||||
EXPORT_SYMBOL(hd64465_gpio_set_port);
|
||||
EXPORT_SYMBOL(hd64465_gpio_unregister_irq);
|
||||
|
||||
/* TODO: each port should be protected with a spinlock */
|
||||
|
||||
|
||||
void hd64465_gpio_configure(int portpin, int direction)
|
||||
{
|
||||
unsigned short cr;
|
||||
unsigned int shift = (_PINOF(portpin)<<1);
|
||||
|
||||
cr = inw(GPIO_CR(_PORTOF(portpin)));
|
||||
cr &= ~(3<<shift);
|
||||
cr |= direction<<shift;
|
||||
outw(cr, GPIO_CR(_PORTOF(portpin)));
|
||||
}
|
||||
|
||||
void hd64465_gpio_set_pin(int portpin, unsigned int value)
|
||||
{
|
||||
unsigned short d;
|
||||
unsigned short mask = 1<<(_PINOF(portpin));
|
||||
|
||||
d = inw(GPIO_DR(_PORTOF(portpin)));
|
||||
if (value)
|
||||
d |= mask;
|
||||
else
|
||||
d &= ~mask;
|
||||
outw(d, GPIO_DR(_PORTOF(portpin)));
|
||||
}
|
||||
|
||||
unsigned int hd64465_gpio_get_pin(int portpin)
|
||||
{
|
||||
return inw(GPIO_DR(_PORTOF(portpin))) & (1<<(_PINOF(portpin)));
|
||||
}
|
||||
|
||||
/* TODO: for cleaner atomicity semantics, add a mask to this routine */
|
||||
|
||||
void hd64465_gpio_set_port(int port, unsigned int value)
|
||||
{
|
||||
outw(value, GPIO_DR(port));
|
||||
}
|
||||
|
||||
unsigned int hd64465_gpio_get_port(int port)
|
||||
{
|
||||
return inw(GPIO_DR(port));
|
||||
}
|
||||
|
||||
|
||||
static struct {
|
||||
void (*func)(int portpin, void *dev);
|
||||
void *dev;
|
||||
} handlers[GPIO_NPORTS * 8];
|
||||
|
||||
static irqreturn_t hd64465_gpio_interrupt(int irq, void *dev)
|
||||
{
|
||||
unsigned short port, pin, isr, mask, portpin;
|
||||
|
||||
for (port=0 ; port<GPIO_NPORTS ; port++) {
|
||||
isr = inw(GPIO_ISR(port));
|
||||
|
||||
for (pin=0 ; pin<8 ; pin++) {
|
||||
mask = 1<<pin;
|
||||
if (isr & mask) {
|
||||
portpin = (port<<3)|pin;
|
||||
if (handlers[portpin].func != 0)
|
||||
handlers[portpin].func(portpin, handlers[portpin].dev);
|
||||
else
|
||||
printk(KERN_NOTICE "unexpected GPIO interrupt, pin %c%d\n",
|
||||
port+'A', (int)pin);
|
||||
}
|
||||
}
|
||||
|
||||
/* Write 1s back to ISR to clear it? That's what the manual says.. */
|
||||
outw(isr, GPIO_ISR(port));
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
void hd64465_gpio_register_irq(int portpin, int mode,
|
||||
void (*handler)(int portpin, void *dev), void *dev)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned short icr, mask;
|
||||
|
||||
if (handler == 0)
|
||||
return;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
handlers[portpin].func = handler;
|
||||
handlers[portpin].dev = dev;
|
||||
|
||||
/*
|
||||
* Configure Interrupt Control Register
|
||||
*/
|
||||
icr = inw(GPIO_ICR(_PORTOF(portpin)));
|
||||
mask = (1<<_PINOF(portpin));
|
||||
|
||||
/* unmask interrupt */
|
||||
icr &= ~mask;
|
||||
|
||||
/* set TS bit */
|
||||
mask <<= 8;
|
||||
icr &= ~mask;
|
||||
if (mode == HD64465_GPIO_RISING)
|
||||
icr |= mask;
|
||||
|
||||
outw(icr, GPIO_ICR(_PORTOF(portpin)));
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
void hd64465_gpio_unregister_irq(int portpin)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned short icr;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
/*
|
||||
* Configure Interrupt Control Register
|
||||
*/
|
||||
icr = inw(GPIO_ICR(_PORTOF(portpin)));
|
||||
icr |= (1<<_PINOF(portpin)); /* mask interrupt */
|
||||
outw(icr, GPIO_ICR(_PORTOF(portpin)));
|
||||
|
||||
handlers[portpin].func = 0;
|
||||
handlers[portpin].dev = 0;
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static int __init hd64465_gpio_init(void)
|
||||
{
|
||||
if (!request_region(HD64465_REG_GPACR, 0x1000, MODNAME))
|
||||
return -EBUSY;
|
||||
if (request_irq(HD64465_IRQ_GPIO, hd64465_gpio_interrupt,
|
||||
IRQF_DISABLED, MODNAME, 0))
|
||||
goto out_irqfailed;
|
||||
|
||||
printk("HD64465 GPIO layer on irq %d\n", HD64465_IRQ_GPIO);
|
||||
|
||||
return 0;
|
||||
|
||||
out_irqfailed:
|
||||
release_region(HD64465_REG_GPACR, 0x1000);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void __exit hd64465_gpio_exit(void)
|
||||
{
|
||||
release_region(HD64465_REG_GPACR, 0x1000);
|
||||
free_irq(HD64465_IRQ_GPIO, 0);
|
||||
}
|
||||
|
||||
module_init(hd64465_gpio_init);
|
||||
module_exit(hd64465_gpio_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -1,211 +0,0 @@
|
|||
/*
|
||||
* $Id: io.c,v 1.4 2003/08/03 03:05:10 lethal Exp $
|
||||
* by Greg Banks <gbanks@pocketpenguins.com>
|
||||
* (c) 2000 PocketPenguins Inc
|
||||
*
|
||||
* Derived from io_hd64461.c, which bore the message:
|
||||
* Copyright (C) 2000 YAEGASHI Takeshi
|
||||
*
|
||||
* Typical I/O routines for HD64465 system.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/hd64465/hd64465.h>
|
||||
|
||||
|
||||
#define HD64465_DEBUG 0
|
||||
|
||||
#if HD64465_DEBUG
|
||||
#define DPRINTK(args...) printk(args)
|
||||
#define DIPRINTK(n, args...) if (hd64465_io_debug>(n)) printk(args)
|
||||
#else
|
||||
#define DPRINTK(args...)
|
||||
#define DIPRINTK(n, args...)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* This is a hack suitable only for debugging IO port problems */
|
||||
int hd64465_io_debug;
|
||||
EXPORT_SYMBOL(hd64465_io_debug);
|
||||
|
||||
/* Low iomap maps port 0-1K to addresses in 8byte chunks */
|
||||
#define HD64465_IOMAP_LO_THRESH 0x400
|
||||
#define HD64465_IOMAP_LO_SHIFT 3
|
||||
#define HD64465_IOMAP_LO_MASK ((1<<HD64465_IOMAP_LO_SHIFT)-1)
|
||||
#define HD64465_IOMAP_LO_NMAP (HD64465_IOMAP_LO_THRESH>>HD64465_IOMAP_LO_SHIFT)
|
||||
static unsigned long hd64465_iomap_lo[HD64465_IOMAP_LO_NMAP];
|
||||
static unsigned char hd64465_iomap_lo_shift[HD64465_IOMAP_LO_NMAP];
|
||||
|
||||
/* High iomap maps port 1K-64K to addresses in 1K chunks */
|
||||
#define HD64465_IOMAP_HI_THRESH 0x10000
|
||||
#define HD64465_IOMAP_HI_SHIFT 10
|
||||
#define HD64465_IOMAP_HI_MASK ((1<<HD64465_IOMAP_HI_SHIFT)-1)
|
||||
#define HD64465_IOMAP_HI_NMAP (HD64465_IOMAP_HI_THRESH>>HD64465_IOMAP_HI_SHIFT)
|
||||
static unsigned long hd64465_iomap_hi[HD64465_IOMAP_HI_NMAP];
|
||||
static unsigned char hd64465_iomap_hi_shift[HD64465_IOMAP_HI_NMAP];
|
||||
|
||||
#define PORT2ADDR(x) (sh_mv.mv_isa_port2addr(x))
|
||||
|
||||
void hd64465_port_map(unsigned short baseport, unsigned int nports,
|
||||
unsigned long addr, unsigned char shift)
|
||||
{
|
||||
unsigned int port, endport = baseport + nports;
|
||||
|
||||
DPRINTK("hd64465_port_map(base=0x%04hx, n=0x%04hx, addr=0x%08lx,endport=0x%04x)\n",
|
||||
baseport, nports, addr,endport);
|
||||
|
||||
for (port = baseport ;
|
||||
port < endport && port < HD64465_IOMAP_LO_THRESH ;
|
||||
port += (1<<HD64465_IOMAP_LO_SHIFT)) {
|
||||
DPRINTK(" maplo[0x%x] = 0x%08lx\n", port, addr);
|
||||
hd64465_iomap_lo[port>>HD64465_IOMAP_LO_SHIFT] = addr;
|
||||
hd64465_iomap_lo_shift[port>>HD64465_IOMAP_LO_SHIFT] = shift;
|
||||
addr += (1<<(HD64465_IOMAP_LO_SHIFT));
|
||||
}
|
||||
|
||||
for (port = max_t(unsigned int, baseport, HD64465_IOMAP_LO_THRESH);
|
||||
port < endport && port < HD64465_IOMAP_HI_THRESH ;
|
||||
port += (1<<HD64465_IOMAP_HI_SHIFT)) {
|
||||
DPRINTK(" maphi[0x%x] = 0x%08lx\n", port, addr);
|
||||
hd64465_iomap_hi[port>>HD64465_IOMAP_HI_SHIFT] = addr;
|
||||
hd64465_iomap_hi_shift[port>>HD64465_IOMAP_HI_SHIFT] = shift;
|
||||
addr += (1<<(HD64465_IOMAP_HI_SHIFT));
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(hd64465_port_map);
|
||||
|
||||
void hd64465_port_unmap(unsigned short baseport, unsigned int nports)
|
||||
{
|
||||
unsigned int port, endport = baseport + nports;
|
||||
|
||||
DPRINTK("hd64465_port_unmap(base=0x%04hx, n=0x%04hx)\n",
|
||||
baseport, nports);
|
||||
|
||||
for (port = baseport ;
|
||||
port < endport && port < HD64465_IOMAP_LO_THRESH ;
|
||||
port += (1<<HD64465_IOMAP_LO_SHIFT)) {
|
||||
hd64465_iomap_lo[port>>HD64465_IOMAP_LO_SHIFT] = 0;
|
||||
}
|
||||
|
||||
for (port = max_t(unsigned int, baseport, HD64465_IOMAP_LO_THRESH);
|
||||
port < endport && port < HD64465_IOMAP_HI_THRESH ;
|
||||
port += (1<<HD64465_IOMAP_HI_SHIFT)) {
|
||||
hd64465_iomap_hi[port>>HD64465_IOMAP_HI_SHIFT] = 0;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(hd64465_port_unmap);
|
||||
|
||||
unsigned long hd64465_isa_port2addr(unsigned long port)
|
||||
{
|
||||
unsigned long addr = 0;
|
||||
unsigned char shift;
|
||||
|
||||
/* handle remapping of low IO ports */
|
||||
if (port < HD64465_IOMAP_LO_THRESH) {
|
||||
addr = hd64465_iomap_lo[port >> HD64465_IOMAP_LO_SHIFT];
|
||||
shift = hd64465_iomap_lo_shift[port >> HD64465_IOMAP_LO_SHIFT];
|
||||
if (addr != 0)
|
||||
addr += (port & HD64465_IOMAP_LO_MASK) << shift;
|
||||
else
|
||||
printk(KERN_NOTICE "io_hd64465: access to un-mapped port %lx\n", port);
|
||||
} else if (port < HD64465_IOMAP_HI_THRESH) {
|
||||
addr = hd64465_iomap_hi[port >> HD64465_IOMAP_HI_SHIFT];
|
||||
shift = hd64465_iomap_hi_shift[port >> HD64465_IOMAP_HI_SHIFT];
|
||||
if (addr != 0)
|
||||
addr += (port & HD64465_IOMAP_HI_MASK) << shift;
|
||||
else
|
||||
printk(KERN_NOTICE "io_hd64465: access to un-mapped port %lx\n", port);
|
||||
}
|
||||
|
||||
/* HD64465 internal devices (0xb0000000) */
|
||||
else if (port < 0x20000)
|
||||
addr = CONFIG_HD64465_IOBASE + port - 0x10000;
|
||||
|
||||
/* Whole physical address space (0xa0000000) */
|
||||
else
|
||||
addr = P2SEGADDR(port);
|
||||
|
||||
DIPRINTK(2, "PORT2ADDR(0x%08lx) = 0x%08lx\n", port, addr);
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
static inline void delay(void)
|
||||
{
|
||||
ctrl_inw(0xa0000000);
|
||||
}
|
||||
|
||||
unsigned char hd64465_inb(unsigned long port)
|
||||
{
|
||||
unsigned long addr = PORT2ADDR(port);
|
||||
unsigned long b = (addr == 0 ? 0 : *(volatile unsigned char*)addr);
|
||||
|
||||
DIPRINTK(0, "inb(%08lx) = %02x\n", addr, (unsigned)b);
|
||||
return b;
|
||||
}
|
||||
|
||||
unsigned char hd64465_inb_p(unsigned long port)
|
||||
{
|
||||
unsigned long v;
|
||||
unsigned long addr = PORT2ADDR(port);
|
||||
|
||||
v = (addr == 0 ? 0 : *(volatile unsigned char*)addr);
|
||||
delay();
|
||||
DIPRINTK(0, "inb_p(%08lx) = %02x\n", addr, (unsigned)v);
|
||||
return v;
|
||||
}
|
||||
|
||||
unsigned short hd64465_inw(unsigned long port)
|
||||
{
|
||||
unsigned long addr = PORT2ADDR(port);
|
||||
unsigned long b = (addr == 0 ? 0 : *(volatile unsigned short*)addr);
|
||||
DIPRINTK(0, "inw(%08lx) = %04lx\n", addr, b);
|
||||
return b;
|
||||
}
|
||||
|
||||
unsigned int hd64465_inl(unsigned long port)
|
||||
{
|
||||
unsigned long addr = PORT2ADDR(port);
|
||||
unsigned int b = (addr == 0 ? 0 : *(volatile unsigned long*)addr);
|
||||
DIPRINTK(0, "inl(%08lx) = %08x\n", addr, b);
|
||||
return b;
|
||||
}
|
||||
|
||||
void hd64465_outb(unsigned char b, unsigned long port)
|
||||
{
|
||||
unsigned long addr = PORT2ADDR(port);
|
||||
|
||||
DIPRINTK(0, "outb(%02x, %08lx)\n", (unsigned)b, addr);
|
||||
if (addr != 0)
|
||||
*(volatile unsigned char*)addr = b;
|
||||
}
|
||||
|
||||
void hd64465_outb_p(unsigned char b, unsigned long port)
|
||||
{
|
||||
unsigned long addr = PORT2ADDR(port);
|
||||
|
||||
DIPRINTK(0, "outb_p(%02x, %08lx)\n", (unsigned)b, addr);
|
||||
if (addr != 0)
|
||||
*(volatile unsigned char*)addr = b;
|
||||
delay();
|
||||
}
|
||||
|
||||
void hd64465_outw(unsigned short b, unsigned long port)
|
||||
{
|
||||
unsigned long addr = PORT2ADDR(port);
|
||||
DIPRINTK(0, "outw(%04x, %08lx)\n", (unsigned)b, addr);
|
||||
if (addr != 0)
|
||||
*(volatile unsigned short*)addr = b;
|
||||
}
|
||||
|
||||
void hd64465_outl(unsigned int b, unsigned long port)
|
||||
{
|
||||
unsigned long addr = PORT2ADDR(port);
|
||||
DIPRINTK(0, "outl(%08x, %08lx)\n", b, addr);
|
||||
if (addr != 0)
|
||||
*(volatile unsigned long*)addr = b;
|
||||
}
|
||||
|
|
@ -1,181 +0,0 @@
|
|||
/*
|
||||
* $Id: setup.c,v 1.4 2003/08/03 03:05:10 lethal Exp $
|
||||
*
|
||||
* Setup and IRQ handling code for the HD64465 companion chip.
|
||||
* by Greg Banks <gbanks@pocketpenguins.com>
|
||||
* Copyright (c) 2000 PocketPenguins Inc
|
||||
*
|
||||
* Derived from setup_hd64461.c which bore the message:
|
||||
* Copyright (C) 2000 YAEGASHI Takeshi
|
||||
*/
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/param.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/hd64465/hd64465.h>
|
||||
|
||||
static void disable_hd64465_irq(unsigned int irq)
|
||||
{
|
||||
unsigned short nimr;
|
||||
unsigned short mask = 1 << (irq - HD64465_IRQ_BASE);
|
||||
|
||||
pr_debug("disable_hd64465_irq(%d): mask=%x\n", irq, mask);
|
||||
nimr = inw(HD64465_REG_NIMR);
|
||||
nimr |= mask;
|
||||
outw(nimr, HD64465_REG_NIMR);
|
||||
}
|
||||
|
||||
static void enable_hd64465_irq(unsigned int irq)
|
||||
{
|
||||
unsigned short nimr;
|
||||
unsigned short mask = 1 << (irq - HD64465_IRQ_BASE);
|
||||
|
||||
pr_debug("enable_hd64465_irq(%d): mask=%x\n", irq, mask);
|
||||
nimr = inw(HD64465_REG_NIMR);
|
||||
nimr &= ~mask;
|
||||
outw(nimr, HD64465_REG_NIMR);
|
||||
}
|
||||
|
||||
static void mask_and_ack_hd64465(unsigned int irq)
|
||||
{
|
||||
disable_hd64465_irq(irq);
|
||||
}
|
||||
|
||||
static void end_hd64465_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
||||
enable_hd64465_irq(irq);
|
||||
}
|
||||
|
||||
static unsigned int startup_hd64465_irq(unsigned int irq)
|
||||
{
|
||||
enable_hd64465_irq(irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void shutdown_hd64465_irq(unsigned int irq)
|
||||
{
|
||||
disable_hd64465_irq(irq);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type hd64465_irq_type = {
|
||||
.typename = "HD64465-IRQ",
|
||||
.startup = startup_hd64465_irq,
|
||||
.shutdown = shutdown_hd64465_irq,
|
||||
.enable = enable_hd64465_irq,
|
||||
.disable = disable_hd64465_irq,
|
||||
.ack = mask_and_ack_hd64465,
|
||||
.end = end_hd64465_irq,
|
||||
};
|
||||
|
||||
static irqreturn_t hd64465_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
printk(KERN_INFO
|
||||
"HD64465: spurious interrupt, nirr: 0x%x nimr: 0x%x\n",
|
||||
inw(HD64465_REG_NIRR), inw(HD64465_REG_NIMR));
|
||||
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Support for a secondary IRQ demux step. This is necessary
|
||||
* because the HD64465 presents a very thin interface to the
|
||||
* PCMCIA bus; a lot of features (such as remapping interrupts)
|
||||
* normally done in hardware by other PCMCIA host bridges is
|
||||
* instead done in software.
|
||||
*/
|
||||
static struct {
|
||||
int (*func)(int, void *);
|
||||
void *dev;
|
||||
} hd64465_demux[HD64465_IRQ_NUM];
|
||||
|
||||
void hd64465_register_irq_demux(int irq,
|
||||
int (*demux)(int irq, void *dev), void *dev)
|
||||
{
|
||||
hd64465_demux[irq - HD64465_IRQ_BASE].func = demux;
|
||||
hd64465_demux[irq - HD64465_IRQ_BASE].dev = dev;
|
||||
}
|
||||
EXPORT_SYMBOL(hd64465_register_irq_demux);
|
||||
|
||||
void hd64465_unregister_irq_demux(int irq)
|
||||
{
|
||||
hd64465_demux[irq - HD64465_IRQ_BASE].func = 0;
|
||||
}
|
||||
EXPORT_SYMBOL(hd64465_unregister_irq_demux);
|
||||
|
||||
int hd64465_irq_demux(int irq)
|
||||
{
|
||||
if (irq == CONFIG_HD64465_IRQ) {
|
||||
unsigned short i, bit;
|
||||
unsigned short nirr = inw(HD64465_REG_NIRR);
|
||||
unsigned short nimr = inw(HD64465_REG_NIMR);
|
||||
|
||||
pr_debug("hd64465_irq_demux, nirr=%04x, nimr=%04x\n", nirr, nimr);
|
||||
nirr &= ~nimr;
|
||||
for (bit = 1, i = 0 ; i < HD64465_IRQ_NUM ; bit <<= 1, i++)
|
||||
if (nirr & bit)
|
||||
break;
|
||||
|
||||
if (i < HD64465_IRQ_NUM) {
|
||||
irq = HD64465_IRQ_BASE + i;
|
||||
if (hd64465_demux[i].func != 0)
|
||||
irq = hd64465_demux[i].func(irq, hd64465_demux[i].dev);
|
||||
}
|
||||
}
|
||||
return irq;
|
||||
}
|
||||
|
||||
static struct irqaction irq0 = {
|
||||
.handler = hd64465_interrupt,
|
||||
.flags = IRQF_DISABLED,
|
||||
.mask = CPU_MASK_NONE,
|
||||
.name = "HD64465",
|
||||
};
|
||||
|
||||
static int __init setup_hd64465(void)
|
||||
{
|
||||
int i;
|
||||
unsigned short rev;
|
||||
unsigned short smscr;
|
||||
|
||||
if (!MACH_HD64465)
|
||||
return 0;
|
||||
|
||||
printk(KERN_INFO "HD64465 configured at 0x%x on irq %d(mapped into %d to %d)\n",
|
||||
CONFIG_HD64465_IOBASE,
|
||||
CONFIG_HD64465_IRQ,
|
||||
HD64465_IRQ_BASE,
|
||||
HD64465_IRQ_BASE+HD64465_IRQ_NUM-1);
|
||||
|
||||
if (inw(HD64465_REG_SDID) != HD64465_SDID) {
|
||||
printk(KERN_ERR "HD64465 device ID not found, check base address\n");
|
||||
}
|
||||
|
||||
rev = inw(HD64465_REG_SRR);
|
||||
printk(KERN_INFO "HD64465 hardware revision %d.%d\n", (rev >> 8) & 0xff, rev & 0xff);
|
||||
|
||||
outw(0xffff, HD64465_REG_NIMR); /* mask all interrupts */
|
||||
|
||||
for (i = 0; i < HD64465_IRQ_NUM ; i++) {
|
||||
irq_desc[HD64465_IRQ_BASE + i].chip = &hd64465_irq_type;
|
||||
}
|
||||
|
||||
setup_irq(CONFIG_HD64465_IRQ, &irq0);
|
||||
|
||||
/* wake up the UART from STANDBY at this point */
|
||||
smscr = inw(HD64465_REG_SMSCR);
|
||||
outw(smscr & (~HD64465_SMSCR_UARTST), HD64465_REG_SMSCR);
|
||||
|
||||
/* remap IO ports for first ISA serial port to HD64465 UART */
|
||||
hd64465_port_map(0x3f8, 8, CONFIG_HD64465_IOBASE + 0x8000, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
module_init(setup_hd64465);
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.27
|
||||
# Tue Oct 21 12:57:28 2008
|
||||
# Linux kernel version: 2.6.28-rc2
|
||||
# Fri Oct 31 15:58:06 2008
|
||||
#
|
||||
CONFIG_SUPERH=y
|
||||
CONFIG_SUPERH32=y
|
||||
|
@ -73,7 +73,6 @@ CONFIG_EVENTFD=y
|
|||
CONFIG_SHMEM=y
|
||||
CONFIG_AIO=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_PCI_QUIRKS=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_SLUB is not set
|
||||
# CONFIG_SLOB is not set
|
||||
|
@ -285,7 +284,7 @@ CONFIG_GUSA=y
|
|||
CONFIG_ZERO_PAGE_OFFSET=0x00001000
|
||||
CONFIG_BOOT_LINK_OFFSET=0x00800000
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=serial ip=on"
|
||||
CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=serial ip=on root=/dev/nfs ip=dhcp"
|
||||
|
||||
#
|
||||
# Bus options
|
||||
|
@ -718,6 +717,7 @@ CONFIG_SSB_POSSIBLE=y
|
|||
# CONFIG_MFD_SM501 is not set
|
||||
# CONFIG_HTC_PASIC3 is not set
|
||||
# CONFIG_MFD_TMIO is not set
|
||||
# CONFIG_PMIC_DA903X is not set
|
||||
# CONFIG_MFD_WM8400 is not set
|
||||
# CONFIG_MFD_WM8350_I2C is not set
|
||||
|
||||
|
@ -969,7 +969,23 @@ CONFIG_TMPFS=y
|
|||
# CONFIG_ROMFS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
# CONFIG_NETWORK_FILESYSTEMS is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
# CONFIG_NFS_V3 is not set
|
||||
# CONFIG_NFS_V4 is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
# CONFIG_SUNRPC_REGISTER_V4 is not set
|
||||
# CONFIG_RPCSEC_GSS_KRB5 is not set
|
||||
# CONFIG_RPCSEC_GSS_SPKM3 is not set
|
||||
# CONFIG_SMB_FS is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
|
@ -1019,7 +1035,12 @@ CONFIG_CRYPTO=y
|
|||
# Crypto core or helper
|
||||
#
|
||||
# CONFIG_CRYPTO_FIPS is not set
|
||||
# CONFIG_CRYPTO_MANAGER is not set
|
||||
CONFIG_CRYPTO_ALGAPI=y
|
||||
CONFIG_CRYPTO_AEAD=y
|
||||
CONFIG_CRYPTO_BLKCIPHER=y
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_RNG=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
# CONFIG_CRYPTO_GF128MUL is not set
|
||||
# CONFIG_CRYPTO_NULL is not set
|
||||
# CONFIG_CRYPTO_CRYPTD is not set
|
||||
|
@ -1096,7 +1117,7 @@ CONFIG_CRYPTO=y
|
|||
# Random Number Generation
|
||||
#
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_HW=y
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
|
|
1169
arch/sh/configs/ul2_defconfig
Normal file
1169
arch/sh/configs/ul2_defconfig
Normal file
File diff suppressed because it is too large
Load diff
|
@ -8,7 +8,15 @@
|
|||
#include <linux/compiler.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
|
||||
#ifdef __LITTLE_ENDIAN__
|
||||
# define __LITTLE_ENDIAN
|
||||
#else
|
||||
# define __BIG_ENDIAN
|
||||
#endif
|
||||
|
||||
#define __SWAB_64_THRU_32__
|
||||
|
||||
static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
|
||||
{
|
||||
__asm__(
|
||||
#ifdef __SH5__
|
||||
|
@ -24,8 +32,9 @@ static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
|
|||
|
||||
return x;
|
||||
}
|
||||
#define __arch_swab32 __arch_swab32
|
||||
|
||||
static inline __attribute_const__ __u16 ___arch__swab16(__u16 x)
|
||||
static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
|
||||
{
|
||||
__asm__(
|
||||
#ifdef __SH5__
|
||||
|
@ -39,32 +48,21 @@ static inline __attribute_const__ __u16 ___arch__swab16(__u16 x)
|
|||
|
||||
return x;
|
||||
}
|
||||
#define __arch_swab16 __arch_swab16
|
||||
|
||||
static inline __u64 ___arch__swab64(__u64 val)
|
||||
static inline __u64 __arch_swab64(__u64 val)
|
||||
{
|
||||
union {
|
||||
struct { __u32 a,b; } s;
|
||||
__u64 u;
|
||||
} v, w;
|
||||
v.u = val;
|
||||
w.s.b = ___arch__swab32(v.s.a);
|
||||
w.s.a = ___arch__swab32(v.s.b);
|
||||
w.s.b = __arch_swab32(v.s.a);
|
||||
w.s.a = __arch_swab32(v.s.b);
|
||||
return w.u;
|
||||
}
|
||||
#define __arch_swab64 __arch_swab64
|
||||
|
||||
#define __arch__swab64(x) ___arch__swab64(x)
|
||||
#define __arch__swab32(x) ___arch__swab32(x)
|
||||
#define __arch__swab16(x) ___arch__swab16(x)
|
||||
|
||||
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
|
||||
# define __BYTEORDER_HAS_U64__
|
||||
# define __SWAB_64_THRU_32__
|
||||
#endif
|
||||
|
||||
#ifdef __LITTLE_ENDIAN__
|
||||
#include <linux/byteorder/little_endian.h>
|
||||
#else
|
||||
#include <linux/byteorder/big_endian.h>
|
||||
#endif
|
||||
#include <linux/byteorder.h>
|
||||
|
||||
#endif /* __ASM_SH_BYTEORDER_H */
|
||||
|
|
|
@ -1,46 +0,0 @@
|
|||
#ifndef _ASM_SH_HD64465_GPIO_
|
||||
#define _ASM_SH_HD64465_GPIO_ 1
|
||||
/*
|
||||
* $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $
|
||||
*
|
||||
* Hitachi HD64465 companion chip: General Purpose IO pins support.
|
||||
* This layer enables other device drivers to configure GPIO
|
||||
* pins, get and set their values, and register an interrupt
|
||||
* routine for when input pins change in hardware.
|
||||
*
|
||||
* by Greg Banks <gbanks@pocketpenguins.com>
|
||||
* (c) 2000 PocketPenguins Inc.
|
||||
*/
|
||||
#include <asm/hd64465.h>
|
||||
|
||||
/* Macro to construct a portpin number (used in all
|
||||
* subsequent functions) from a port letter and a pin
|
||||
* number, e.g. HD64465_GPIO_PORTPIN('A', 5).
|
||||
*/
|
||||
#define HD64465_GPIO_PORTPIN(port,pin) (((port)-'A')<<3|(pin))
|
||||
|
||||
/* Pin configuration constants for _configure() */
|
||||
#define HD64465_GPIO_FUNCTION2 0 /* use the pin's *other* function */
|
||||
#define HD64465_GPIO_OUT 1 /* output */
|
||||
#define HD64465_GPIO_IN_PULLUP 2 /* input, pull-up MOS on */
|
||||
#define HD64465_GPIO_IN 3 /* input */
|
||||
|
||||
/* Configure a pin's direction */
|
||||
extern void hd64465_gpio_configure(int portpin, int direction);
|
||||
|
||||
/* Get, set value */
|
||||
extern void hd64465_gpio_set_pin(int portpin, unsigned int value);
|
||||
extern unsigned int hd64465_gpio_get_pin(int portpin);
|
||||
extern void hd64465_gpio_set_port(int port, unsigned int value);
|
||||
extern unsigned int hd64465_gpio_get_port(int port);
|
||||
|
||||
/* mode constants for _register_irq() */
|
||||
#define HD64465_GPIO_FALLING 0
|
||||
#define HD64465_GPIO_RISING 1
|
||||
|
||||
/* Interrupt on external value change */
|
||||
extern void hd64465_gpio_register_irq(int portpin, int mode,
|
||||
void (*handler)(int portpin, void *dev), void *dev);
|
||||
extern void hd64465_gpio_unregister_irq(int portpin);
|
||||
|
||||
#endif /* _ASM_SH_HD64465_GPIO_ */
|
|
@ -1,256 +0,0 @@
|
|||
#ifndef _ASM_SH_HD64465_
|
||||
#define _ASM_SH_HD64465_ 1
|
||||
/*
|
||||
* $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $
|
||||
*
|
||||
* Hitachi HD64465 companion chip support
|
||||
*
|
||||
* by Greg Banks <gbanks@pocketpenguins.com>
|
||||
* (c) 2000 PocketPenguins Inc.
|
||||
*
|
||||
* Derived from <asm/hd64461.h> which bore the message:
|
||||
* Copyright (C) 2000 YAEGASHI Takeshi
|
||||
*/
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
/*
|
||||
* Note that registers are defined here as virtual port numbers,
|
||||
* which have no meaning except to get translated by hd64465_isa_port2addr()
|
||||
* to an address in the range 0xb0000000-0xb3ffffff. Note that
|
||||
* this translation happens to consist of adding the lower 16 bits
|
||||
* of the virtual port number to 0xb0000000. Note also that the manual
|
||||
* shows addresses as absolute physical addresses starting at 0x10000000,
|
||||
* so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the
|
||||
* manual, and accessed using address 0xb0005000 - Greg.
|
||||
*/
|
||||
|
||||
/* System registers */
|
||||
#define HD64465_REG_SRR 0x1000c /* System Revision Register */
|
||||
#define HD64465_REG_SDID 0x10010 /* System Device ID Reg */
|
||||
#define HD64465_SDID 0x8122 /* 64465 device ID */
|
||||
|
||||
/* Power Management registers */
|
||||
#define HD64465_REG_SMSCR 0x10000 /* System Module Standby Control Reg */
|
||||
#define HD64465_SMSCR_PS2ST 0x4000 /* PS/2 Standby */
|
||||
#define HD64465_SMSCR_ADCST 0x1000 /* ADC Standby */
|
||||
#define HD64465_SMSCR_UARTST 0x0800 /* UART Standby */
|
||||
#define HD64465_SMSCR_SCDIST 0x0200 /* Serial Codec Standby */
|
||||
#define HD64465_SMSCR_PPST 0x0100 /* Parallel Port Standby */
|
||||
#define HD64465_SMSCR_PC0ST 0x0040 /* PCMCIA0 Standby */
|
||||
#define HD64465_SMSCR_PC1ST 0x0020 /* PCMCIA1 Standby */
|
||||
#define HD64465_SMSCR_AFEST 0x0010 /* AFE Standby */
|
||||
#define HD64465_SMSCR_TM0ST 0x0008 /* Timer0 Standby */
|
||||
#define HD64465_SMSCR_TM1ST 0x0004 /* Timer1 Standby */
|
||||
#define HD64465_SMSCR_IRDAST 0x0002 /* IRDA Standby */
|
||||
#define HD64465_SMSCR_KBCST 0x0001 /* Keyboard Controller Standby */
|
||||
|
||||
/* Interrupt Controller registers */
|
||||
#define HD64465_REG_NIRR 0x15000 /* Interrupt Request Register */
|
||||
#define HD64465_REG_NIMR 0x15002 /* Interrupt Mask Register */
|
||||
#define HD64465_REG_NITR 0x15004 /* Interrupt Trigger Mode Register */
|
||||
|
||||
/* Timer registers */
|
||||
#define HD64465_REG_TCVR1 0x16000 /* Timer 1 constant value register */
|
||||
#define HD64465_REG_TCVR0 0x16002 /* Timer 0 constant value register */
|
||||
#define HD64465_REG_TRVR1 0x16004 /* Timer 1 read value register */
|
||||
#define HD64465_REG_TRVR0 0x16006 /* Timer 0 read value register */
|
||||
#define HD64465_REG_TCR1 0x16008 /* Timer 1 control register */
|
||||
#define HD64465_REG_TCR0 0x1600A /* Timer 0 control register */
|
||||
#define HD64465_TCR_EADT 0x10 /* Enable ADTRIG# signal */
|
||||
#define HD64465_TCR_ETMO 0x08 /* Enable TMO signal */
|
||||
#define HD64465_TCR_PST_MASK 0x06 /* Clock Prescale */
|
||||
#define HD64465_TCR_PST_1 0x06 /* 1:1 */
|
||||
#define HD64465_TCR_PST_4 0x04 /* 1:4 */
|
||||
#define HD64465_TCR_PST_8 0x02 /* 1:8 */
|
||||
#define HD64465_TCR_PST_16 0x00 /* 1:16 */
|
||||
#define HD64465_TCR_TSTP 0x01 /* Start/Stop timer */
|
||||
#define HD64465_REG_TIRR 0x1600C /* Timer interrupt request register */
|
||||
#define HD64465_REG_TIDR 0x1600E /* Timer interrupt disable register */
|
||||
#define HD64465_REG_PWM1CS 0x16010 /* PWM 1 clock scale register */
|
||||
#define HD64465_REG_PWM1LPC 0x16012 /* PWM 1 low pulse width counter register */
|
||||
#define HD64465_REG_PWM1HPC 0x16014 /* PWM 1 high pulse width counter register */
|
||||
#define HD64465_REG_PWM0CS 0x16018 /* PWM 0 clock scale register */
|
||||
#define HD64465_REG_PWM0LPC 0x1601A /* PWM 0 low pulse width counter register */
|
||||
#define HD64465_REG_PWM0HPC 0x1601C /* PWM 0 high pulse width counter register */
|
||||
|
||||
/* Analog/Digital Converter registers */
|
||||
#define HD64465_REG_ADDRA 0x1E000 /* A/D data register A */
|
||||
#define HD64465_REG_ADDRB 0x1E002 /* A/D data register B */
|
||||
#define HD64465_REG_ADDRC 0x1E004 /* A/D data register C */
|
||||
#define HD64465_REG_ADDRD 0x1E006 /* A/D data register D */
|
||||
#define HD64465_REG_ADCSR 0x1E008 /* A/D control/status register */
|
||||
#define HD64465_ADCSR_ADF 0x80 /* A/D End Flag */
|
||||
#define HD64465_ADCSR_ADST 0x40 /* A/D Start Flag */
|
||||
#define HD64465_ADCSR_ADIS 0x20 /* A/D Interrupt Status */
|
||||
#define HD64465_ADCSR_TRGE 0x10 /* A/D Trigger Enable */
|
||||
#define HD64465_ADCSR_ADIE 0x08 /* A/D Interrupt Enable */
|
||||
#define HD64465_ADCSR_SCAN 0x04 /* A/D Scan Mode */
|
||||
#define HD64465_ADCSR_CH_MASK 0x03 /* A/D Channel */
|
||||
#define HD64465_REG_ADCALCR 0x1E00A /* A/D calibration sample control */
|
||||
#define HD64465_REG_ADCAL 0x1E00C /* A/D calibration data register */
|
||||
|
||||
|
||||
/* General Purpose I/O ports registers */
|
||||
#define HD64465_REG_GPACR 0x14000 /* Port A Control Register */
|
||||
#define HD64465_REG_GPBCR 0x14002 /* Port B Control Register */
|
||||
#define HD64465_REG_GPCCR 0x14004 /* Port C Control Register */
|
||||
#define HD64465_REG_GPDCR 0x14006 /* Port D Control Register */
|
||||
#define HD64465_REG_GPECR 0x14008 /* Port E Control Register */
|
||||
#define HD64465_REG_GPADR 0x14010 /* Port A Data Register */
|
||||
#define HD64465_REG_GPBDR 0x14012 /* Port B Data Register */
|
||||
#define HD64465_REG_GPCDR 0x14014 /* Port C Data Register */
|
||||
#define HD64465_REG_GPDDR 0x14016 /* Port D Data Register */
|
||||
#define HD64465_REG_GPEDR 0x14018 /* Port E Data Register */
|
||||
#define HD64465_REG_GPAICR 0x14020 /* Port A Interrupt Control Register */
|
||||
#define HD64465_REG_GPBICR 0x14022 /* Port B Interrupt Control Register */
|
||||
#define HD64465_REG_GPCICR 0x14024 /* Port C Interrupt Control Register */
|
||||
#define HD64465_REG_GPDICR 0x14026 /* Port D Interrupt Control Register */
|
||||
#define HD64465_REG_GPEICR 0x14028 /* Port E Interrupt Control Register */
|
||||
#define HD64465_REG_GPAISR 0x14040 /* Port A Interrupt Status Register */
|
||||
#define HD64465_REG_GPBISR 0x14042 /* Port B Interrupt Status Register */
|
||||
#define HD64465_REG_GPCISR 0x14044 /* Port C Interrupt Status Register */
|
||||
#define HD64465_REG_GPDISR 0x14046 /* Port D Interrupt Status Register */
|
||||
#define HD64465_REG_GPEISR 0x14048 /* Port E Interrupt Status Register */
|
||||
|
||||
/* PCMCIA bridge interface */
|
||||
#define HD64465_REG_PCC0ISR 0x12000 /* socket 0 interface status */
|
||||
#define HD64465_PCCISR_PREADY 0x80 /* mem card ready / io card IREQ */
|
||||
#define HD64465_PCCISR_PIREQ 0x80
|
||||
#define HD64465_PCCISR_PMWP 0x40 /* mem card write-protected */
|
||||
#define HD64465_PCCISR_PVS2 0x20 /* voltage select pin 2 */
|
||||
#define HD64465_PCCISR_PVS1 0x10 /* voltage select pin 1 */
|
||||
#define HD64465_PCCISR_PCD_MASK 0x0c /* card detect */
|
||||
#define HD64465_PCCISR_PBVD_MASK 0x03 /* battery voltage */
|
||||
#define HD64465_PCCISR_PBVD_BATGOOD 0x03 /* battery good */
|
||||
#define HD64465_PCCISR_PBVD_BATWARN 0x01 /* battery low warning */
|
||||
#define HD64465_PCCISR_PBVD_BATDEAD1 0x02 /* battery dead */
|
||||
#define HD64465_PCCISR_PBVD_BATDEAD2 0x00 /* battery dead */
|
||||
#define HD64465_REG_PCC0GCR 0x12002 /* socket 0 general control */
|
||||
#define HD64465_PCCGCR_PDRV 0x80 /* output drive */
|
||||
#define HD64465_PCCGCR_PCCR 0x40 /* PC card reset */
|
||||
#define HD64465_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
|
||||
#define HD64465_PCCGCR_PVCC0 0x10 /* voltage control pin VCC0SEL0 */
|
||||
#define HD64465_PCCGCR_PMMOD 0x08 /* memory mode */
|
||||
#define HD64465_PCCGCR_PPA25 0x04 /* pin A25 */
|
||||
#define HD64465_PCCGCR_PPA24 0x02 /* pin A24 */
|
||||
#define HD64465_PCCGCR_PREG 0x01 /* ping PCC0REG# */
|
||||
#define HD64465_REG_PCC0CSCR 0x12004 /* socket 0 card status change */
|
||||
#define HD64465_PCCCSCR_PSCDI 0x80 /* sw card detect intr */
|
||||
#define HD64465_PCCCSCR_PSWSEL 0x40 /* power select */
|
||||
#define HD64465_PCCCSCR_PIREQ 0x20 /* IREQ intr req */
|
||||
#define HD64465_PCCCSCR_PSC 0x10 /* STSCHG (status change) pin */
|
||||
#define HD64465_PCCCSCR_PCDC 0x08 /* CD (card detect) change */
|
||||
#define HD64465_PCCCSCR_PRC 0x04 /* ready change */
|
||||
#define HD64465_PCCCSCR_PBW 0x02 /* battery warning change */
|
||||
#define HD64465_PCCCSCR_PBD 0x01 /* battery dead change */
|
||||
#define HD64465_REG_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
|
||||
#define HD64465_PCCCSCIER_PCRE 0x80 /* change reset enable */
|
||||
#define HD64465_PCCCSCIER_PIREQE_MASK 0x60 /* IREQ enable */
|
||||
#define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 /* IREQ disabled */
|
||||
#define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 /* IREQ level-triggered */
|
||||
#define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 /* IREQ falling-edge-trig */
|
||||
#define HD64465_PCCCSCIER_PIREQE_RISING 0x60 /* IREQ rising-edge-trig */
|
||||
#define HD64465_PCCCSCIER_PSCE 0x10 /* status change enable */
|
||||
#define HD64465_PCCCSCIER_PCDE 0x08 /* card detect change enable */
|
||||
#define HD64465_PCCCSCIER_PRE 0x04 /* ready change enable */
|
||||
#define HD64465_PCCCSCIER_PBWE 0x02 /* battery warn change enable */
|
||||
#define HD64465_PCCCSCIER_PBDE 0x01 /* battery dead change enable*/
|
||||
#define HD64465_REG_PCC0SCR 0x12008 /* socket 0 software control */
|
||||
#define HD64465_PCCSCR_SHDN 0x10 /* TPS2206 SHutDowN pin */
|
||||
#define HD64465_PCCSCR_SWP 0x01 /* write protect */
|
||||
#define HD64465_REG_PCCPSR 0x1200A /* serial power switch control */
|
||||
#define HD64465_REG_PCC1ISR 0x12010 /* socket 1 interface status */
|
||||
#define HD64465_REG_PCC1GCR 0x12012 /* socket 1 general control */
|
||||
#define HD64465_REG_PCC1CSCR 0x12014 /* socket 1 card status change */
|
||||
#define HD64465_REG_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
|
||||
#define HD64465_REG_PCC1SCR 0x12018 /* socket 1 software control */
|
||||
|
||||
|
||||
/* PS/2 Keyboard and mouse controller -- *not* register compatible */
|
||||
#define HD64465_REG_KBCSR 0x1dc00 /* Keyboard Control/Status reg */
|
||||
#define HD64465_KBCSR_KBCIE 0x8000 /* KBCK Input Enable */
|
||||
#define HD64465_KBCSR_KBCOE 0x4000 /* KBCK Output Enable */
|
||||
#define HD64465_KBCSR_KBDOE 0x2000 /* KB DATA Output Enable */
|
||||
#define HD64465_KBCSR_KBCD 0x1000 /* KBCK Driven */
|
||||
#define HD64465_KBCSR_KBDD 0x0800 /* KB DATA Driven */
|
||||
#define HD64465_KBCSR_KBCS 0x0400 /* KBCK pin Status */
|
||||
#define HD64465_KBCSR_KBDS 0x0200 /* KB DATA pin Status */
|
||||
#define HD64465_KBCSR_KBDP 0x0100 /* KB DATA Parity bit */
|
||||
#define HD64465_KBCSR_KBD_MASK 0x00ff /* KD DATA shift reg */
|
||||
#define HD64465_REG_KBISR 0x1dc04 /* Keyboard Interrupt Status reg */
|
||||
#define HD64465_KBISR_KBRDF 0x0001 /* KB Received Data Full */
|
||||
#define HD64465_REG_MSCSR 0x1dc10 /* Mouse Control/Status reg */
|
||||
#define HD64465_REG_MSISR 0x1dc14 /* Mouse Interrupt Status reg */
|
||||
|
||||
|
||||
/*
|
||||
* Logical address at which the HD64465 is mapped. Note that this
|
||||
* should always be in the P2 segment (uncached and untranslated).
|
||||
*/
|
||||
#ifndef CONFIG_HD64465_IOBASE
|
||||
#define CONFIG_HD64465_IOBASE 0xb0000000
|
||||
#endif
|
||||
/*
|
||||
* The HD64465 multiplexes all its modules' interrupts onto
|
||||
* this single interrupt.
|
||||
*/
|
||||
#ifndef CONFIG_HD64465_IRQ
|
||||
#define CONFIG_HD64465_IRQ 5
|
||||
#endif
|
||||
|
||||
|
||||
#define _HD64465_IO_MASK 0xf8000000
|
||||
#define is_hd64465_addr(addr) \
|
||||
((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK))
|
||||
|
||||
/*
|
||||
* A range of 16 virtual interrupts generated by
|
||||
* demuxing the HD64465 muxed interrupt.
|
||||
*/
|
||||
#define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE
|
||||
#define HD64465_IRQ_NUM 16
|
||||
#define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0)
|
||||
#define HD64465_IRQ_USB (HD64465_IRQ_BASE+1)
|
||||
#define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2)
|
||||
#define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3)
|
||||
/* bit 4 is reserved */
|
||||
#define HD64465_IRQ_UART (HD64465_IRQ_BASE+5)
|
||||
#define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6)
|
||||
#define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7)
|
||||
#define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8)
|
||||
#define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9)
|
||||
#define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10)
|
||||
#define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11)
|
||||
#define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12)
|
||||
#define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13)
|
||||
#define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14)
|
||||
#define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15)
|
||||
|
||||
/* Constants for PCMCIA mappings */
|
||||
#define HD64465_PCC_WINDOW 0x01000000
|
||||
|
||||
#define HD64465_PCC0_BASE 0xb8000000 /* area 6 */
|
||||
#define HD64465_PCC0_ATTR (HD64465_PCC0_BASE)
|
||||
#define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW)
|
||||
#define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW)
|
||||
|
||||
#define HD64465_PCC1_BASE 0xb4000000 /* area 5 */
|
||||
#define HD64465_PCC1_ATTR (HD64465_PCC1_BASE)
|
||||
#define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW)
|
||||
#define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW)
|
||||
|
||||
/*
|
||||
* Base of USB controller interface (as memory)
|
||||
*/
|
||||
#define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000)
|
||||
#define HD64465_USB_LEN 0x1000
|
||||
/*
|
||||
* Base of embedded SRAM, used for USB controller.
|
||||
*/
|
||||
#define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000)
|
||||
#define HD64465_SRAM_LEN 0x1000
|
||||
|
||||
|
||||
|
||||
#endif /* _ASM_SH_HD64465_ */
|
|
@ -1,44 +0,0 @@
|
|||
/*
|
||||
* include/asm-sh/hd64465/io.h
|
||||
*
|
||||
* By Greg Banks <gbanks@pocketpenguins.com>
|
||||
* (c) 2000 PocketPenguins Inc.
|
||||
*
|
||||
* Derived from io_hd64461.h, which bore the message:
|
||||
* Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
|
||||
*
|
||||
* May be copied or modified under the terms of the GNU General Public
|
||||
* License. See linux/COPYING for more information.
|
||||
*
|
||||
* IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller".
|
||||
*/
|
||||
|
||||
#ifndef _ASM_SH_IO_HD64465_H
|
||||
#define _ASM_SH_IO_HD64465_H
|
||||
|
||||
extern unsigned char hd64465_inb(unsigned long port);
|
||||
extern unsigned short hd64465_inw(unsigned long port);
|
||||
extern unsigned int hd64465_inl(unsigned long port);
|
||||
|
||||
extern void hd64465_outb(unsigned char value, unsigned long port);
|
||||
extern void hd64465_outw(unsigned short value, unsigned long port);
|
||||
extern void hd64465_outl(unsigned int value, unsigned long port);
|
||||
|
||||
extern unsigned char hd64465_inb_p(unsigned long port);
|
||||
extern void hd64465_outb_p(unsigned char value, unsigned long port);
|
||||
|
||||
extern unsigned long hd64465_isa_port2addr(unsigned long offset);
|
||||
extern int hd64465_irq_demux(int irq);
|
||||
/* Provision for generic secondary demux step -- used by PCMCIA code */
|
||||
extern void hd64465_register_irq_demux(int irq,
|
||||
int (*demux)(int irq, void *dev), void *dev);
|
||||
extern void hd64465_unregister_irq_demux(int irq);
|
||||
/* Set this variable to 1 to see port traffic */
|
||||
extern int hd64465_io_debug;
|
||||
/* Map a range of ports to a range of kernel virtual memory.
|
||||
*/
|
||||
extern void hd64465_port_map(unsigned short baseport, unsigned int nports,
|
||||
unsigned long addr, unsigned char shift);
|
||||
extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports);
|
||||
|
||||
#endif /* _ASM_SH_IO_HD64465_H */
|
|
@ -7,8 +7,6 @@
|
|||
#ifndef _ASM_SERIAL_H
|
||||
#define _ASM_SERIAL_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
/*
|
||||
* This assumes you have a 1.8432 MHz clock for your UART.
|
||||
*
|
||||
|
@ -18,19 +16,4 @@
|
|||
*/
|
||||
#define BASE_BAUD ( 1843200 / 16 )
|
||||
|
||||
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
|
||||
|
||||
#ifdef CONFIG_HD64465
|
||||
#include <asm/hd64465/hd64465.h>
|
||||
|
||||
#define SERIAL_PORT_DFNS \
|
||||
/* UART CLK PORT IRQ FLAGS */ \
|
||||
{ 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
|
||||
|
||||
#else
|
||||
|
||||
#define SERIAL_PORT_DFNS
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_SERIAL_H */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#ifndef __ASM_SH_CPU_SH4_RTC_H
|
||||
#define __ASM_SH_CPU_SH4_RTC_H
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7723
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
#define rtc_reg_size sizeof(u16)
|
||||
#else
|
||||
#define rtc_reg_size sizeof(u32)
|
||||
|
|
|
@ -36,6 +36,32 @@ static struct platform_device iic_device = {
|
|||
.resource = iic_resources,
|
||||
};
|
||||
|
||||
static struct resource usb_host_resources[] = {
|
||||
[0] = {
|
||||
.name = "r8a66597_hcd",
|
||||
.start = 0xa4d80000,
|
||||
.end = 0xa4d800ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.name = "r8a66597_hcd",
|
||||
.start = 65,
|
||||
.end = 65,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device usb_host_device = {
|
||||
.name = "r8a66597_hcd",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = NULL,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(usb_host_resources),
|
||||
.resource = usb_host_resources,
|
||||
};
|
||||
|
||||
static struct uio_info vpu_platform_data = {
|
||||
.name = "VPU5",
|
||||
.version = "0",
|
||||
|
@ -142,6 +168,7 @@ static struct platform_device sci_device = {
|
|||
static struct platform_device *sh7366_devices[] __initdata = {
|
||||
&iic_device,
|
||||
&sci_device,
|
||||
&usb_host_device,
|
||||
&vpu_device,
|
||||
&veu0_device,
|
||||
&veu1_device,
|
||||
|
@ -158,6 +185,7 @@ static int __init sh7366_devices_setup(void)
|
|||
clk_always_enable("mstp022"); /* INTC */
|
||||
clk_always_enable("mstp020"); /* SuperHyway */
|
||||
clk_always_enable("mstp109"); /* I2C */
|
||||
clk_always_enable("mstp211"); /* USB */
|
||||
clk_always_enable("mstp207"); /* VEU-2 */
|
||||
clk_always_enable("mstp202"); /* VEU-1 */
|
||||
clk_always_enable("mstp201"); /* VPU */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* SH7722 Setup
|
||||
*
|
||||
* Copyright (C) 2006 - 2007 Paul Mundt
|
||||
* Copyright (C) 2006 - 2008 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
@ -16,6 +16,36 @@
|
|||
#include <asm/clock.h>
|
||||
#include <asm/mmzone.h>
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xa465fec0,
|
||||
.end = 0xa465fec0 + 0x58 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Period IRQ */
|
||||
.start = 45,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* Carry IRQ */
|
||||
.start = 46,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
/* Alarm IRQ */
|
||||
.start = 44,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "sh-rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resource = rtc_resources,
|
||||
};
|
||||
|
||||
static struct resource usbf_resources[] = {
|
||||
[0] = {
|
||||
.name = "m66592_udc",
|
||||
|
@ -150,6 +180,7 @@ static struct platform_device sci_device = {
|
|||
};
|
||||
|
||||
static struct platform_device *sh7722_devices[] __initdata = {
|
||||
&rtc_device,
|
||||
&usbf_device,
|
||||
&iic_device,
|
||||
&sci_device,
|
||||
|
@ -202,7 +233,6 @@ enum {
|
|||
IRDA, JPU, LCDC,
|
||||
|
||||
/* interrupt groups */
|
||||
|
||||
SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
|
||||
};
|
||||
|
||||
|
|
|
@ -372,7 +372,7 @@ syscall_exit:
|
|||
7: .long do_syscall_trace_enter
|
||||
8: .long do_syscall_trace_leave
|
||||
|
||||
#ifdef CONFIG_FTRACE
|
||||
#ifdef CONFIG_FUNCTION_TRACER
|
||||
.align 2
|
||||
.globl _mcount
|
||||
.type _mcount,@function
|
||||
|
@ -414,4 +414,4 @@ skip_trace:
|
|||
ftrace_stub:
|
||||
rts
|
||||
nop
|
||||
#endif /* CONFIG_FTRACE */
|
||||
#endif /* CONFIG_FUNCTION_TRACER */
|
||||
|
|
|
@ -50,7 +50,10 @@ EXPORT_SYMBOL(__udelay);
|
|||
EXPORT_SYMBOL(__ndelay);
|
||||
EXPORT_SYMBOL(__const_udelay);
|
||||
|
||||
#define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name)
|
||||
#define DECLARE_EXPORT(name) \
|
||||
extern void name(void);EXPORT_SYMBOL(name)
|
||||
#define MAYBE_DECLARE_EXPORT(name) \
|
||||
extern void name(void) __weak;EXPORT_SYMBOL(name)
|
||||
|
||||
/* These symbols are generated by the compiler itself */
|
||||
DECLARE_EXPORT(__udivsi3);
|
||||
|
@ -109,10 +112,8 @@ DECLARE_EXPORT(__movmemSI12_i4);
|
|||
* compiler which include backported patches.
|
||||
*/
|
||||
DECLARE_EXPORT(__udiv_qrnnd_16);
|
||||
#if !defined(CONFIG_CPU_SH2)
|
||||
DECLARE_EXPORT(__sdivsi3_i4i);
|
||||
DECLARE_EXPORT(__udivsi3_i4i);
|
||||
#endif
|
||||
MAYBE_DECLARE_EXPORT(__sdivsi3_i4i);
|
||||
MAYBE_DECLARE_EXPORT(__udivsi3_i4i);
|
||||
#endif
|
||||
#else /* GCC 3.x */
|
||||
DECLARE_EXPORT(__movstr_i4_even);
|
||||
|
@ -133,7 +134,7 @@ EXPORT_SYMBOL(flush_dcache_page);
|
|||
EXPORT_SYMBOL(clear_user_page);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FTRACE
|
||||
#ifdef CONFIG_FUNCTION_TRACER
|
||||
EXPORT_SYMBOL(mcount);
|
||||
#endif
|
||||
EXPORT_SYMBOL(csum_partial);
|
||||
|
|
|
@ -59,7 +59,7 @@ void __flush_purge_region(void *start, int size)
|
|||
|
||||
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
|
||||
ctrl_outl((v & CACHE_PHYSADDR_MASK),
|
||||
CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
|
||||
CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
|
||||
}
|
||||
back_to_cached();
|
||||
local_irq_restore(flags);
|
||||
|
@ -82,14 +82,14 @@ void __flush_invalidate_region(void *start, int size)
|
|||
/* I-cache invalidate */
|
||||
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
|
||||
ctrl_outl((v & CACHE_PHYSADDR_MASK),
|
||||
CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
|
||||
CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
|
||||
}
|
||||
#else
|
||||
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
|
||||
ctrl_outl((v & CACHE_PHYSADDR_MASK),
|
||||
CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
|
||||
CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
|
||||
ctrl_outl((v & CACHE_PHYSADDR_MASK),
|
||||
CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
|
||||
CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
|
||||
}
|
||||
#endif
|
||||
back_to_cached();
|
||||
|
|
|
@ -255,10 +255,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
|
|||
return -ENODEV;
|
||||
|
||||
ops = &sh7750_perf_counter_ops;
|
||||
ops->cpu_type = (char *)get_cpu_subtype(¤t_cpu_data);
|
||||
ops->cpu_type = "sh/sh7750";
|
||||
|
||||
printk(KERN_INFO "oprofile: using SH-4 (%s) performance monitoring.\n",
|
||||
sh7750_perf_counter_ops.cpu_type);
|
||||
printk(KERN_INFO "oprofile: using SH-4 performance monitoring.\n");
|
||||
|
||||
/* Clear the counters */
|
||||
ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1);
|
||||
|
@ -270,4 +269,3 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
|
|||
void oprofile_arch_exit(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
|
@ -13,7 +13,6 @@ RTS7751R2D SH_RTS7751R2D
|
|||
# List of companion chips / MFDs.
|
||||
#
|
||||
HD64461 HD64461
|
||||
HD64465 HD64465
|
||||
|
||||
#
|
||||
# List of boards.
|
||||
|
|
|
@ -495,9 +495,10 @@ static int gdrom_bdops_open(struct block_device *bdev, fmode_t mode)
|
|||
return cdrom_open(gd.cd_info, bdev, mode);
|
||||
}
|
||||
|
||||
static int gdrom_bdops_release(struct block_device *bdev, fmode_t mode)
|
||||
static int gdrom_bdops_release(struct gendisk *disk, fmode_t mode)
|
||||
{
|
||||
return cdrom_release(gd.cd_info, mode);
|
||||
cdrom_release(gd.cd_info, mode);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gdrom_bdops_mediachanged(struct gendisk *disk)
|
||||
|
|
|
@ -188,10 +188,6 @@ config PCMCIA_M8XX
|
|||
|
||||
This driver is also available as a module called m8xx_pcmcia.
|
||||
|
||||
config HD64465_PCMCIA
|
||||
tristate "HD64465 host bridge support"
|
||||
depends on HD64465 && PCMCIA
|
||||
|
||||
config PCMCIA_AU1X00
|
||||
tristate "Au1x00 pcmcia support"
|
||||
depends on SOC_AU1X00 && PCMCIA
|
||||
|
|
|
@ -22,7 +22,6 @@ obj-$(CONFIG_I82365) += i82365.o
|
|||
obj-$(CONFIG_I82092) += i82092.o
|
||||
obj-$(CONFIG_TCIC) += tcic.o
|
||||
obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
|
||||
obj-$(CONFIG_HD64465_PCMCIA) += hd64465_ss.o
|
||||
obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_core.o sa1100_cs.o
|
||||
obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o
|
||||
obj-$(CONFIG_M32R_PCC) += m32r_pcc.o
|
||||
|
|
|
@ -1,939 +0,0 @@
|
|||
/*
|
||||
* Device driver for the PCMCIA controller module of the
|
||||
* Hitachi HD64465 handheld companion chip.
|
||||
*
|
||||
* Note that the HD64465 provides a very thin PCMCIA host bridge
|
||||
* layer, requiring a lot of the work of supporting cards to be
|
||||
* performed by the processor. For example: mapping of card
|
||||
* interrupts to processor IRQs is done by IRQ demuxing software;
|
||||
* IO and memory mappings are fixed; setting voltages according
|
||||
* to card Voltage Select pins etc is done in software.
|
||||
*
|
||||
* Note also that this driver uses only the simple, fixed,
|
||||
* 16MB, 16-bit wide mappings to PCMCIA spaces defined by the
|
||||
* HD64465. Larger mappings, smaller mappings, or mappings of
|
||||
* different width to the same socket, are all possible only by
|
||||
* involving the SH7750's MMU, which is considered unnecessary here.
|
||||
* The downside is that it may be possible for some drivers to
|
||||
* break because they need or expect 8-bit mappings.
|
||||
*
|
||||
* This driver currently supports only the following configuration:
|
||||
* SH7750 CPU, HD64465, TPS2206 voltage control chip.
|
||||
*
|
||||
* by Greg Banks <gbanks@pocketpenguins.com>
|
||||
* (c) 2000 PocketPenguins Inc
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <asm/errno.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/hd64465/hd64465.h>
|
||||
#include <asm/hd64465/io.h>
|
||||
|
||||
#include <pcmcia/cs_types.h>
|
||||
#include <pcmcia/cs.h>
|
||||
#include <pcmcia/cistpl.h>
|
||||
#include <pcmcia/ds.h>
|
||||
#include <pcmcia/ss.h>
|
||||
|
||||
#define MODNAME "hd64465_ss"
|
||||
|
||||
/* #define HD64465_DEBUG 1 */
|
||||
|
||||
#if HD64465_DEBUG
|
||||
#define DPRINTK(args...) printk(MODNAME ": " args)
|
||||
#else
|
||||
#define DPRINTK(args...)
|
||||
#endif
|
||||
|
||||
extern int hd64465_io_debug;
|
||||
extern void * p3_ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags);
|
||||
extern void p3_iounmap(void *addr);
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
#define HS_IO_MAP_SIZE (64*1024)
|
||||
|
||||
typedef struct hs_socket_t
|
||||
{
|
||||
unsigned int number;
|
||||
u_int irq;
|
||||
u_long mem_base;
|
||||
void *io_base;
|
||||
u_long mem_length;
|
||||
u_int ctrl_base;
|
||||
socket_state_t state;
|
||||
pccard_io_map io_maps[MAX_IO_WIN];
|
||||
pccard_mem_map mem_maps[MAX_WIN];
|
||||
struct pcmcia_socket socket;
|
||||
} hs_socket_t;
|
||||
|
||||
|
||||
|
||||
#define HS_MAX_SOCKETS 2
|
||||
static hs_socket_t hs_sockets[HS_MAX_SOCKETS];
|
||||
|
||||
#define hs_in(sp, r) inb((sp)->ctrl_base + (r))
|
||||
#define hs_out(sp, v, r) outb(v, (sp)->ctrl_base + (r))
|
||||
|
||||
|
||||
/* translate a boolean value to a bit in a register */
|
||||
#define bool_to_regbit(sp, r, bi, bo) \
|
||||
do { \
|
||||
unsigned short v = hs_in(sp, r); \
|
||||
if (bo) \
|
||||
v |= (bi); \
|
||||
else \
|
||||
v &= ~(bi); \
|
||||
hs_out(sp, v, r); \
|
||||
} while(0)
|
||||
|
||||
/* register offsets from HD64465_REG_PCC[01]ISR */
|
||||
#define ISR 0x0
|
||||
#define GCR 0x2
|
||||
#define CSCR 0x4
|
||||
#define CSCIER 0x6
|
||||
#define SCR 0x8
|
||||
|
||||
|
||||
/* Mask and values for CSCIER register */
|
||||
#define IER_MASK 0x80
|
||||
#define IER_ON 0x3f /* interrupts on */
|
||||
#define IER_OFF 0x00 /* interrupts off */
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
#if HD64465_DEBUG > 10
|
||||
|
||||
static void cis_hex_dump(const unsigned char *x, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0 ; i<len ; i++)
|
||||
{
|
||||
if (!(i & 0xf))
|
||||
printk("\n%08x", (unsigned)(x + i));
|
||||
printk(" %02x", *(volatile unsigned short*)x);
|
||||
x += 2;
|
||||
}
|
||||
printk("\n");
|
||||
}
|
||||
|
||||
#endif
|
||||
/*============================================================*/
|
||||
|
||||
/*
|
||||
* This code helps create the illusion that the IREQ line from
|
||||
* the PC card is mapped to one of the CPU's IRQ lines by the
|
||||
* host bridge hardware (which is how every host bridge *except*
|
||||
* the HD64465 works). In particular, it supports enabling
|
||||
* and disabling the IREQ line by code which knows nothing
|
||||
* about the host bridge (e.g. device drivers, IDE code) using
|
||||
* the request_irq(), free_irq(), probe_irq_on() and probe_irq_off()
|
||||
* functions. Also, it supports sharing the mapped IRQ with
|
||||
* real hardware IRQs from the -IRL0-3 lines.
|
||||
*/
|
||||
|
||||
#define HS_NUM_MAPPED_IRQS 16 /* Limitation of the PCMCIA code */
|
||||
static struct
|
||||
{
|
||||
/* index is mapped irq number */
|
||||
hs_socket_t *sock;
|
||||
hw_irq_controller *old_handler;
|
||||
} hs_mapped_irq[HS_NUM_MAPPED_IRQS];
|
||||
|
||||
static void hs_socket_enable_ireq(hs_socket_t *sp)
|
||||
{
|
||||
unsigned short cscier;
|
||||
|
||||
DPRINTK("hs_socket_enable_ireq(sock=%d)\n", sp->number);
|
||||
|
||||
cscier = hs_in(sp, CSCIER);
|
||||
cscier &= ~HD64465_PCCCSCIER_PIREQE_MASK;
|
||||
cscier |= HD64465_PCCCSCIER_PIREQE_LEVEL;
|
||||
hs_out(sp, cscier, CSCIER);
|
||||
}
|
||||
|
||||
static void hs_socket_disable_ireq(hs_socket_t *sp)
|
||||
{
|
||||
unsigned short cscier;
|
||||
|
||||
DPRINTK("hs_socket_disable_ireq(sock=%d)\n", sp->number);
|
||||
|
||||
cscier = hs_in(sp, CSCIER);
|
||||
cscier &= ~HD64465_PCCCSCIER_PIREQE_MASK;
|
||||
hs_out(sp, cscier, CSCIER);
|
||||
}
|
||||
|
||||
static unsigned int hs_startup_irq(unsigned int irq)
|
||||
{
|
||||
hs_socket_enable_ireq(hs_mapped_irq[irq].sock);
|
||||
hs_mapped_irq[irq].old_handler->startup(irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hs_shutdown_irq(unsigned int irq)
|
||||
{
|
||||
hs_socket_disable_ireq(hs_mapped_irq[irq].sock);
|
||||
hs_mapped_irq[irq].old_handler->shutdown(irq);
|
||||
}
|
||||
|
||||
static void hs_enable_irq(unsigned int irq)
|
||||
{
|
||||
hs_socket_enable_ireq(hs_mapped_irq[irq].sock);
|
||||
hs_mapped_irq[irq].old_handler->enable(irq);
|
||||
}
|
||||
|
||||
static void hs_disable_irq(unsigned int irq)
|
||||
{
|
||||
hs_socket_disable_ireq(hs_mapped_irq[irq].sock);
|
||||
hs_mapped_irq[irq].old_handler->disable(irq);
|
||||
}
|
||||
|
||||
extern struct hw_interrupt_type no_irq_type;
|
||||
|
||||
static void hs_mask_and_ack_irq(unsigned int irq)
|
||||
{
|
||||
hs_socket_disable_ireq(hs_mapped_irq[irq].sock);
|
||||
/* ack_none() spuriously complains about an unexpected IRQ */
|
||||
if (hs_mapped_irq[irq].old_handler != &no_irq_type)
|
||||
hs_mapped_irq[irq].old_handler->ack(irq);
|
||||
}
|
||||
|
||||
static void hs_end_irq(unsigned int irq)
|
||||
{
|
||||
hs_socket_enable_ireq(hs_mapped_irq[irq].sock);
|
||||
hs_mapped_irq[irq].old_handler->end(irq);
|
||||
}
|
||||
|
||||
|
||||
static struct hw_interrupt_type hd64465_ss_irq_type = {
|
||||
.typename = "PCMCIA-IRQ",
|
||||
.startup = hs_startup_irq,
|
||||
.shutdown = hs_shutdown_irq,
|
||||
.enable = hs_enable_irq,
|
||||
.disable = hs_disable_irq,
|
||||
.ack = hs_mask_and_ack_irq,
|
||||
.end = hs_end_irq
|
||||
};
|
||||
|
||||
/*
|
||||
* This function should only ever be called with interrupts disabled.
|
||||
*/
|
||||
static void hs_map_irq(hs_socket_t *sp, unsigned int irq)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
|
||||
DPRINTK("hs_map_irq(sock=%d irq=%d)\n", sp->number, irq);
|
||||
|
||||
if (irq >= HS_NUM_MAPPED_IRQS)
|
||||
return;
|
||||
|
||||
desc = irq_to_desc(irq);
|
||||
hs_mapped_irq[irq].sock = sp;
|
||||
/* insert ourselves as the irq controller */
|
||||
hs_mapped_irq[irq].old_handler = desc->chip;
|
||||
desc->chip = &hd64465_ss_irq_type;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* This function should only ever be called with interrupts disabled.
|
||||
*/
|
||||
static void hs_unmap_irq(hs_socket_t *sp, unsigned int irq)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
|
||||
DPRINTK("hs_unmap_irq(sock=%d irq=%d)\n", sp->number, irq);
|
||||
|
||||
if (irq >= HS_NUM_MAPPED_IRQS)
|
||||
return;
|
||||
|
||||
desc = irq_to_desc(irq);
|
||||
/* restore the original irq controller */
|
||||
desc->chip = hs_mapped_irq[irq].old_handler;
|
||||
}
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
|
||||
/*
|
||||
* Set Vpp and Vcc (in tenths of a Volt). Does not
|
||||
* support the hi-Z state.
|
||||
*
|
||||
* Note, this assumes the board uses a TPS2206 chip to control
|
||||
* the Vcc and Vpp voltages to the hs_sockets. If your board
|
||||
* uses the MIC2563 (also supported by the HD64465) then you
|
||||
* will have to modify this function.
|
||||
*/
|
||||
/* 0V 3.3V 5.5V */
|
||||
static const u_char hs_tps2206_avcc[3] = { 0x00, 0x04, 0x08 };
|
||||
static const u_char hs_tps2206_bvcc[3] = { 0x00, 0x80, 0x40 };
|
||||
|
||||
static int hs_set_voltages(hs_socket_t *sp, int Vcc, int Vpp)
|
||||
{
|
||||
u_int psr;
|
||||
u_int vcci = 0;
|
||||
u_int sock = sp->number;
|
||||
|
||||
DPRINTK("hs_set_voltage(%d, %d, %d)\n", sock, Vcc, Vpp);
|
||||
|
||||
switch (Vcc)
|
||||
{
|
||||
case 0: vcci = 0; break;
|
||||
case 33: vcci = 1; break;
|
||||
case 50: vcci = 2; break;
|
||||
default: return 0;
|
||||
}
|
||||
|
||||
/* Note: Vpp = 120 not supported -- Greg Banks */
|
||||
if (Vpp != 0 && Vpp != Vcc)
|
||||
return 0;
|
||||
|
||||
/* The PSR register holds 8 of the 9 bits which control
|
||||
* the TPS2206 via its serial interface.
|
||||
*/
|
||||
psr = inw(HD64465_REG_PCCPSR);
|
||||
switch (sock)
|
||||
{
|
||||
case 0:
|
||||
psr &= 0x0f;
|
||||
psr |= hs_tps2206_avcc[vcci];
|
||||
psr |= (Vpp == 0 ? 0x00 : 0x02);
|
||||
break;
|
||||
case 1:
|
||||
psr &= 0xf0;
|
||||
psr |= hs_tps2206_bvcc[vcci];
|
||||
psr |= (Vpp == 0 ? 0x00 : 0x20);
|
||||
break;
|
||||
};
|
||||
outw(psr, HD64465_REG_PCCPSR);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
/*
|
||||
* Drive the RESET line to the card.
|
||||
*/
|
||||
static void hs_reset_socket(hs_socket_t *sp, int on)
|
||||
{
|
||||
unsigned short v;
|
||||
|
||||
v = hs_in(sp, GCR);
|
||||
if (on)
|
||||
v |= HD64465_PCCGCR_PCCR;
|
||||
else
|
||||
v &= ~HD64465_PCCGCR_PCCR;
|
||||
hs_out(sp, v, GCR);
|
||||
}
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
static int hs_init(struct pcmcia_socket *s)
|
||||
{
|
||||
hs_socket_t *sp = container_of(s, struct hs_socket_t, socket);
|
||||
|
||||
DPRINTK("hs_init(%d)\n", sp->number);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
|
||||
static int hs_get_status(struct pcmcia_socket *s, u_int *value)
|
||||
{
|
||||
hs_socket_t *sp = container_of(s, struct hs_socket_t, socket);
|
||||
unsigned int isr;
|
||||
u_int status = 0;
|
||||
|
||||
|
||||
isr = hs_in(sp, ISR);
|
||||
|
||||
/* Card is seated and powered when *both* CD pins are low */
|
||||
if ((isr & HD64465_PCCISR_PCD_MASK) == 0)
|
||||
{
|
||||
status |= SS_DETECT; /* card present */
|
||||
|
||||
switch (isr & HD64465_PCCISR_PBVD_MASK)
|
||||
{
|
||||
case HD64465_PCCISR_PBVD_BATGOOD:
|
||||
break;
|
||||
case HD64465_PCCISR_PBVD_BATWARN:
|
||||
status |= SS_BATWARN;
|
||||
break;
|
||||
default:
|
||||
status |= SS_BATDEAD;
|
||||
break;
|
||||
}
|
||||
|
||||
if (isr & HD64465_PCCISR_PREADY)
|
||||
status |= SS_READY;
|
||||
|
||||
if (isr & HD64465_PCCISR_PMWP)
|
||||
status |= SS_WRPROT;
|
||||
|
||||
/* Voltage Select pins interpreted as per Table 4-5 of the std.
|
||||
* Assuming we have the TPS2206, the socket is a "Low Voltage
|
||||
* key, 3.3V and 5V available, no X.XV available".
|
||||
*/
|
||||
switch (isr & (HD64465_PCCISR_PVS2|HD64465_PCCISR_PVS1))
|
||||
{
|
||||
case HD64465_PCCISR_PVS1:
|
||||
printk(KERN_NOTICE MODNAME ": cannot handle X.XV card, ignored\n");
|
||||
status = 0;
|
||||
break;
|
||||
case 0:
|
||||
case HD64465_PCCISR_PVS2:
|
||||
/* 3.3V */
|
||||
status |= SS_3VCARD;
|
||||
break;
|
||||
case HD64465_PCCISR_PVS2|HD64465_PCCISR_PVS1:
|
||||
/* 5V */
|
||||
break;
|
||||
}
|
||||
|
||||
/* TODO: SS_POWERON */
|
||||
/* TODO: SS_STSCHG */
|
||||
}
|
||||
|
||||
DPRINTK("hs_get_status(%d) = %x\n", sock, status);
|
||||
|
||||
*value = status;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
static int hs_set_socket(struct pcmcia_socket *s, socket_state_t *state)
|
||||
{
|
||||
hs_socket_t *sp = container_of(s, struct hs_socket_t, socket);
|
||||
u_long flags;
|
||||
u_int changed;
|
||||
unsigned short cscier;
|
||||
|
||||
DPRINTK("hs_set_socket(sock=%d, flags=%x, csc_mask=%x, Vcc=%d, Vpp=%d, io_irq=%d)\n",
|
||||
sock, state->flags, state->csc_mask, state->Vcc, state->Vpp, state->io_irq);
|
||||
|
||||
local_irq_save(flags); /* Don't want interrupts happening here */
|
||||
|
||||
if (state->Vpp != sp->state.Vpp ||
|
||||
state->Vcc != sp->state.Vcc) {
|
||||
if (!hs_set_voltages(sp, state->Vcc, state->Vpp)) {
|
||||
local_irq_restore(flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* hd64465_io_debug = 1; */
|
||||
/*
|
||||
* Handle changes in the Card Status Change mask,
|
||||
* by propagating to the CSCR register
|
||||
*/
|
||||
changed = sp->state.csc_mask ^ state->csc_mask;
|
||||
cscier = hs_in(sp, CSCIER);
|
||||
|
||||
if (changed & SS_DETECT) {
|
||||
if (state->csc_mask & SS_DETECT)
|
||||
cscier |= HD64465_PCCCSCIER_PCDE;
|
||||
else
|
||||
cscier &= ~HD64465_PCCCSCIER_PCDE;
|
||||
}
|
||||
|
||||
if (changed & SS_READY) {
|
||||
if (state->csc_mask & SS_READY)
|
||||
cscier |= HD64465_PCCCSCIER_PRE;
|
||||
else
|
||||
cscier &= ~HD64465_PCCCSCIER_PRE;
|
||||
}
|
||||
|
||||
if (changed & SS_BATDEAD) {
|
||||
if (state->csc_mask & SS_BATDEAD)
|
||||
cscier |= HD64465_PCCCSCIER_PBDE;
|
||||
else
|
||||
cscier &= ~HD64465_PCCCSCIER_PBDE;
|
||||
}
|
||||
|
||||
if (changed & SS_BATWARN) {
|
||||
if (state->csc_mask & SS_BATWARN)
|
||||
cscier |= HD64465_PCCCSCIER_PBWE;
|
||||
else
|
||||
cscier &= ~HD64465_PCCCSCIER_PBWE;
|
||||
}
|
||||
|
||||
if (changed & SS_STSCHG) {
|
||||
if (state->csc_mask & SS_STSCHG)
|
||||
cscier |= HD64465_PCCCSCIER_PSCE;
|
||||
else
|
||||
cscier &= ~HD64465_PCCCSCIER_PSCE;
|
||||
}
|
||||
|
||||
hs_out(sp, cscier, CSCIER);
|
||||
|
||||
if (sp->state.io_irq && !state->io_irq)
|
||||
hs_unmap_irq(sp, sp->state.io_irq);
|
||||
else if (!sp->state.io_irq && state->io_irq)
|
||||
hs_map_irq(sp, state->io_irq);
|
||||
|
||||
|
||||
/*
|
||||
* Handle changes in the flags field,
|
||||
* by propagating to config registers.
|
||||
*/
|
||||
changed = sp->state.flags ^ state->flags;
|
||||
|
||||
if (changed & SS_IOCARD) {
|
||||
DPRINTK("card type: %s\n",
|
||||
(state->flags & SS_IOCARD ? "i/o" : "memory" ));
|
||||
bool_to_regbit(sp, GCR, HD64465_PCCGCR_PCCT,
|
||||
state->flags & SS_IOCARD);
|
||||
}
|
||||
|
||||
if (changed & SS_RESET) {
|
||||
DPRINTK("%s reset card\n",
|
||||
(state->flags & SS_RESET ? "start" : "stop"));
|
||||
bool_to_regbit(sp, GCR, HD64465_PCCGCR_PCCR,
|
||||
state->flags & SS_RESET);
|
||||
}
|
||||
|
||||
if (changed & SS_OUTPUT_ENA) {
|
||||
DPRINTK("%sabling card output\n",
|
||||
(state->flags & SS_OUTPUT_ENA ? "en" : "dis"));
|
||||
bool_to_regbit(sp, GCR, HD64465_PCCGCR_PDRV,
|
||||
state->flags & SS_OUTPUT_ENA);
|
||||
}
|
||||
|
||||
/* TODO: SS_SPKR_ENA */
|
||||
|
||||
/* hd64465_io_debug = 0; */
|
||||
sp->state = *state;
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
#if HD64465_DEBUG > 10
|
||||
if (state->flags & SS_OUTPUT_ENA)
|
||||
cis_hex_dump((const unsigned char*)sp->mem_base, 0x100);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
static int hs_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
|
||||
{
|
||||
hs_socket_t *sp = container_of(s, struct hs_socket_t, socket);
|
||||
int map = io->map;
|
||||
int sock = sp->number;
|
||||
struct pccard_io_map *sio;
|
||||
pgprot_t prot;
|
||||
|
||||
DPRINTK("hs_set_io_map(sock=%d, map=%d, flags=0x%x, speed=%dns, start=%#lx, stop=%#lx)\n",
|
||||
sock, map, io->flags, io->speed, io->start, io->stop);
|
||||
if (map >= MAX_IO_WIN)
|
||||
return -EINVAL;
|
||||
sio = &sp->io_maps[map];
|
||||
|
||||
/* check for null changes */
|
||||
if (io->flags == sio->flags &&
|
||||
io->start == sio->start &&
|
||||
io->stop == sio->stop)
|
||||
return 0;
|
||||
|
||||
if (io->flags & MAP_AUTOSZ)
|
||||
prot = PAGE_KERNEL_PCC(sock, _PAGE_PCC_IODYN);
|
||||
else if (io->flags & MAP_16BIT)
|
||||
prot = PAGE_KERNEL_PCC(sock, _PAGE_PCC_IO16);
|
||||
else
|
||||
prot = PAGE_KERNEL_PCC(sock, _PAGE_PCC_IO8);
|
||||
|
||||
/* TODO: handle MAP_USE_WAIT */
|
||||
if (io->flags & MAP_USE_WAIT)
|
||||
printk(KERN_INFO MODNAME ": MAP_USE_WAIT unimplemented\n");
|
||||
/* TODO: handle MAP_PREFETCH */
|
||||
if (io->flags & MAP_PREFETCH)
|
||||
printk(KERN_INFO MODNAME ": MAP_PREFETCH unimplemented\n");
|
||||
/* TODO: handle MAP_WRPROT */
|
||||
if (io->flags & MAP_WRPROT)
|
||||
printk(KERN_INFO MODNAME ": MAP_WRPROT unimplemented\n");
|
||||
/* TODO: handle MAP_0WS */
|
||||
if (io->flags & MAP_0WS)
|
||||
printk(KERN_INFO MODNAME ": MAP_0WS unimplemented\n");
|
||||
|
||||
if (io->flags & MAP_ACTIVE) {
|
||||
unsigned long pstart, psize, paddrbase;
|
||||
|
||||
paddrbase = virt_to_phys((void*)(sp->mem_base + 2 * HD64465_PCC_WINDOW));
|
||||
pstart = io->start & PAGE_MASK;
|
||||
psize = ((io->stop + PAGE_SIZE) & PAGE_MASK) - pstart;
|
||||
|
||||
/*
|
||||
* Change PTEs in only that portion of the mapping requested
|
||||
* by the caller. This means that most of the time, most of
|
||||
* the PTEs in the io_vma will be unmapped and only the bottom
|
||||
* page will be mapped. But the code allows for weird cards
|
||||
* that might want IO ports > 4K.
|
||||
*/
|
||||
sp->io_base = p3_ioremap(paddrbase + pstart, psize, pgprot_val(prot));
|
||||
|
||||
/*
|
||||
* Change the mapping used by inb() outb() etc
|
||||
*/
|
||||
hd64465_port_map(io->start,
|
||||
io->stop - io->start + 1,
|
||||
(unsigned long)sp->io_base + io->start, 0);
|
||||
} else {
|
||||
hd64465_port_unmap(sio->start, sio->stop - sio->start + 1);
|
||||
p3_iounmap(sp->io_base);
|
||||
}
|
||||
|
||||
*sio = *io;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
static int hs_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
|
||||
{
|
||||
hs_socket_t *sp = container_of(s, struct hs_socket_t, socket);
|
||||
struct pccard_mem_map *smem;
|
||||
int map = mem->map;
|
||||
unsigned long paddr;
|
||||
|
||||
#if 0
|
||||
DPRINTK("hs_set_mem_map(sock=%d, map=%d, flags=0x%x, card_start=0x%08x)\n",
|
||||
sock, map, mem->flags, mem->card_start);
|
||||
#endif
|
||||
|
||||
if (map >= MAX_WIN)
|
||||
return -EINVAL;
|
||||
smem = &sp->mem_maps[map];
|
||||
|
||||
paddr = sp->mem_base; /* base of Attribute mapping */
|
||||
if (!(mem->flags & MAP_ATTRIB))
|
||||
paddr += HD64465_PCC_WINDOW; /* base of Common mapping */
|
||||
paddr += mem->card_start;
|
||||
|
||||
/* Because we specified SS_CAP_STATIC_MAP, we are obliged
|
||||
* at this time to report the system address corresponding
|
||||
* to the card address requested. This is how Socket Services
|
||||
* queries our fixed mapping. I wish this fact had been
|
||||
* documented - Greg Banks.
|
||||
*/
|
||||
mem->static_start = paddr;
|
||||
|
||||
*smem = *mem;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* TODO: do we need to use the MMU to access Common memory ??? */
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
/*
|
||||
* This function is registered with the HD64465 glue code to do a
|
||||
* secondary demux step on the PCMCIA interrupts. It handles
|
||||
* mapping the IREQ request from the card to a standard Linux
|
||||
* IRQ, as requested by SocketServices.
|
||||
*/
|
||||
static int hs_irq_demux(int irq, void *dev)
|
||||
{
|
||||
hs_socket_t *sp = dev;
|
||||
u_int cscr;
|
||||
|
||||
DPRINTK("hs_irq_demux(irq=%d)\n", irq);
|
||||
|
||||
if (sp->state.io_irq &&
|
||||
(cscr = hs_in(sp, CSCR)) & HD64465_PCCCSCR_PIREQ) {
|
||||
cscr &= ~HD64465_PCCCSCR_PIREQ;
|
||||
hs_out(sp, cscr, CSCR);
|
||||
return sp->state.io_irq;
|
||||
}
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
/*
|
||||
* Interrupt handling routine.
|
||||
*/
|
||||
|
||||
static irqreturn_t hs_interrupt(int irq, void *dev)
|
||||
{
|
||||
hs_socket_t *sp = dev;
|
||||
u_int events = 0;
|
||||
u_int cscr;
|
||||
|
||||
cscr = hs_in(sp, CSCR);
|
||||
|
||||
DPRINTK("hs_interrupt, cscr=%04x\n", cscr);
|
||||
|
||||
/* check for bus-related changes to be reported to Socket Services */
|
||||
if (cscr & HD64465_PCCCSCR_PCDC) {
|
||||
/* double-check for a 16-bit card, as we don't support CardBus */
|
||||
if ((hs_in(sp, ISR) & HD64465_PCCISR_PCD_MASK) != 0) {
|
||||
printk(KERN_NOTICE MODNAME
|
||||
": socket %d, card not a supported card type or not inserted correctly\n",
|
||||
sp->number);
|
||||
/* Don't do the rest unless a card is present */
|
||||
cscr &= ~(HD64465_PCCCSCR_PCDC|
|
||||
HD64465_PCCCSCR_PRC|
|
||||
HD64465_PCCCSCR_PBW|
|
||||
HD64465_PCCCSCR_PBD|
|
||||
HD64465_PCCCSCR_PSC);
|
||||
} else {
|
||||
cscr &= ~HD64465_PCCCSCR_PCDC;
|
||||
events |= SS_DETECT; /* card insertion or removal */
|
||||
}
|
||||
}
|
||||
if (cscr & HD64465_PCCCSCR_PRC) {
|
||||
cscr &= ~HD64465_PCCCSCR_PRC;
|
||||
events |= SS_READY; /* ready signal changed */
|
||||
}
|
||||
if (cscr & HD64465_PCCCSCR_PBW) {
|
||||
cscr &= ~HD64465_PCCCSCR_PSC;
|
||||
events |= SS_BATWARN; /* battery warning */
|
||||
}
|
||||
if (cscr & HD64465_PCCCSCR_PBD) {
|
||||
cscr &= ~HD64465_PCCCSCR_PSC;
|
||||
events |= SS_BATDEAD; /* battery dead */
|
||||
}
|
||||
if (cscr & HD64465_PCCCSCR_PSC) {
|
||||
cscr &= ~HD64465_PCCCSCR_PSC;
|
||||
events |= SS_STSCHG; /* STSCHG (status changed) signal */
|
||||
}
|
||||
|
||||
if (cscr & HD64465_PCCCSCR_PIREQ) {
|
||||
cscr &= ~HD64465_PCCCSCR_PIREQ;
|
||||
|
||||
/* This should have been dealt with during irq demux */
|
||||
printk(KERN_NOTICE MODNAME ": unexpected IREQ from card\n");
|
||||
}
|
||||
|
||||
hs_out(sp, cscr, CSCR);
|
||||
|
||||
if (events)
|
||||
pcmcia_parse_events(&sp->socket, events);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/*============================================================*/
|
||||
|
||||
static struct pccard_operations hs_operations = {
|
||||
.init = hs_init,
|
||||
.get_status = hs_get_status,
|
||||
.set_socket = hs_set_socket,
|
||||
.set_io_map = hs_set_io_map,
|
||||
.set_mem_map = hs_set_mem_map,
|
||||
};
|
||||
|
||||
static int hs_init_socket(hs_socket_t *sp, int irq, unsigned long mem_base,
|
||||
unsigned int ctrl_base)
|
||||
{
|
||||
unsigned short v;
|
||||
int i, err;
|
||||
|
||||
memset(sp, 0, sizeof(*sp));
|
||||
sp->irq = irq;
|
||||
sp->mem_base = mem_base;
|
||||
sp->mem_length = 4*HD64465_PCC_WINDOW; /* 16MB */
|
||||
sp->ctrl_base = ctrl_base;
|
||||
|
||||
for (i=0 ; i<MAX_IO_WIN ; i++)
|
||||
sp->io_maps[i].map = i;
|
||||
for (i=0 ; i<MAX_WIN ; i++)
|
||||
sp->mem_maps[i].map = i;
|
||||
|
||||
hd64465_register_irq_demux(sp->irq, hs_irq_demux, sp);
|
||||
|
||||
if ((err = request_irq(sp->irq, hs_interrupt, IRQF_DISABLED, MODNAME, sp)) < 0)
|
||||
return err;
|
||||
if (request_mem_region(sp->mem_base, sp->mem_length, MODNAME) == 0) {
|
||||
sp->mem_base = 0;
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
||||
/* According to section 3.2 of the PCMCIA standard, low-voltage
|
||||
* capable cards must implement cold insertion, i.e. Vpp and
|
||||
* Vcc set to 0 before card is inserted.
|
||||
*/
|
||||
/*hs_set_voltages(sp, 0, 0);*/
|
||||
|
||||
/* hi-Z the outputs to the card and set 16MB map mode */
|
||||
v = hs_in(sp, GCR);
|
||||
v &= ~HD64465_PCCGCR_PCCT; /* memory-only card */
|
||||
hs_out(sp, v, GCR);
|
||||
|
||||
v = hs_in(sp, GCR);
|
||||
v |= HD64465_PCCGCR_PDRV; /* enable outputs to card */
|
||||
hs_out(sp, v, GCR);
|
||||
|
||||
v = hs_in(sp, GCR);
|
||||
v |= HD64465_PCCGCR_PMMOD; /* 16MB mapping mode */
|
||||
hs_out(sp, v, GCR);
|
||||
|
||||
v = hs_in(sp, GCR);
|
||||
/* lowest 16MB of Common */
|
||||
v &= ~(HD64465_PCCGCR_PPA25|HD64465_PCCGCR_PPA24);
|
||||
hs_out(sp, v, GCR);
|
||||
|
||||
hs_reset_socket(sp, 1);
|
||||
|
||||
printk(KERN_INFO "HD64465 PCMCIA bridge socket %d at 0x%08lx irq %d\n",
|
||||
i, sp->mem_base, sp->irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hs_exit_socket(hs_socket_t *sp)
|
||||
{
|
||||
unsigned short cscier, gcr;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
/* turn off interrupts in hardware */
|
||||
cscier = hs_in(sp, CSCIER);
|
||||
cscier = (cscier & IER_MASK) | IER_OFF;
|
||||
hs_out(sp, cscier, CSCIER);
|
||||
|
||||
/* hi-Z the outputs to the card */
|
||||
gcr = hs_in(sp, GCR);
|
||||
gcr &= HD64465_PCCGCR_PDRV;
|
||||
hs_out(sp, gcr, GCR);
|
||||
|
||||
/* power the card down */
|
||||
hs_set_voltages(sp, 0, 0);
|
||||
|
||||
if (sp->mem_base != 0)
|
||||
release_mem_region(sp->mem_base, sp->mem_length);
|
||||
if (sp->irq != 0) {
|
||||
free_irq(sp->irq, hs_interrupt);
|
||||
hd64465_unregister_irq_demux(sp->irq);
|
||||
}
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static struct device_driver hd64465_driver = {
|
||||
.name = "hd64465-pcmcia",
|
||||
.bus = &platform_bus_type,
|
||||
.suspend = pcmcia_socket_dev_suspend,
|
||||
.resume = pcmcia_socket_dev_resume,
|
||||
};
|
||||
|
||||
static struct platform_device hd64465_device = {
|
||||
.name = "hd64465-pcmcia",
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
static int __init init_hs(void)
|
||||
{
|
||||
int i;
|
||||
unsigned short v;
|
||||
|
||||
/* hd64465_io_debug = 1; */
|
||||
if (driver_register(&hd64465_driver))
|
||||
return -EINVAL;
|
||||
|
||||
/* Wake both sockets out of STANDBY mode */
|
||||
/* TODO: wait 15ms */
|
||||
v = inw(HD64465_REG_SMSCR);
|
||||
v &= ~(HD64465_SMSCR_PC0ST|HD64465_SMSCR_PC1ST);
|
||||
outw(v, HD64465_REG_SMSCR);
|
||||
|
||||
/* keep power controller out of shutdown mode */
|
||||
v = inb(HD64465_REG_PCC0SCR);
|
||||
v |= HD64465_PCCSCR_SHDN;
|
||||
outb(v, HD64465_REG_PCC0SCR);
|
||||
|
||||
/* use serial (TPS2206) power controller */
|
||||
v = inb(HD64465_REG_PCC0CSCR);
|
||||
v |= HD64465_PCCCSCR_PSWSEL;
|
||||
outb(v, HD64465_REG_PCC0CSCR);
|
||||
|
||||
/*
|
||||
* Setup hs_sockets[] structures and request system resources.
|
||||
* TODO: on memory allocation failure, power down the socket
|
||||
* before quitting.
|
||||
*/
|
||||
for (i=0; i<HS_MAX_SOCKETS; i++) {
|
||||
hs_set_voltages(&hs_sockets[i], 0, 0);
|
||||
|
||||
hs_sockets[i].socket.features |= SS_CAP_PCCARD | SS_CAP_STATIC_MAP; /* mappings are fixed in host memory */
|
||||
hs_sockets[i].socket.resource_ops = &pccard_static_ops;
|
||||
hs_sockets[i].socket.irq_mask = 0xffde;/*0xffff*/ /* IRQs mapped in s/w so can do any, really */
|
||||
hs_sockets[i].socket.map_size = HD64465_PCC_WINDOW; /* 16MB fixed window size */
|
||||
|
||||
hs_sockets[i].socket.owner = THIS_MODULE;
|
||||
hs_sockets[i].socket.ss_entry = &hs_operations;
|
||||
}
|
||||
|
||||
i = hs_init_socket(&hs_sockets[0],
|
||||
HD64465_IRQ_PCMCIA0,
|
||||
HD64465_PCC0_BASE,
|
||||
HD64465_REG_PCC0ISR);
|
||||
if (i < 0) {
|
||||
unregister_driver(&hd64465_driver);
|
||||
return i;
|
||||
}
|
||||
i = hs_init_socket(&hs_sockets[1],
|
||||
HD64465_IRQ_PCMCIA1,
|
||||
HD64465_PCC1_BASE,
|
||||
HD64465_REG_PCC1ISR);
|
||||
if (i < 0) {
|
||||
unregister_driver(&hd64465_driver);
|
||||
return i;
|
||||
}
|
||||
|
||||
/* hd64465_io_debug = 0; */
|
||||
|
||||
platform_device_register(&hd64465_device);
|
||||
|
||||
for (i=0; i<HS_MAX_SOCKETS; i++) {
|
||||
unsigned int ret;
|
||||
hs_sockets[i].socket.dev.parent = &hd64465_device.dev;
|
||||
hs_sockets[i].number = i;
|
||||
ret = pcmcia_register_socket(&hs_sockets[i].socket);
|
||||
if (ret && i)
|
||||
pcmcia_unregister_socket(&hs_sockets[0].socket);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit exit_hs(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0 ; i<HS_MAX_SOCKETS ; i++) {
|
||||
pcmcia_unregister_socket(&hs_sockets[i].socket);
|
||||
hs_exit_socket(&hs_sockets[i]);
|
||||
}
|
||||
|
||||
platform_device_unregister(&hd64465_device);
|
||||
unregister_driver(&hd64465_driver);
|
||||
}
|
||||
|
||||
module_init(init_hs);
|
||||
module_exit(exit_hs);
|
||||
|
||||
/*============================================================*/
|
||||
/*END*/
|
|
@ -250,8 +250,7 @@ static inline void h8300_sci_disable(struct uart_port *port)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
|
||||
defined(__H8300H__) || defined(__H8300S__)
|
||||
#if defined(__H8300H__) || defined(__H8300S__)
|
||||
static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
|
||||
{
|
||||
int ch = (port->mapbase - SMR0) >> 3;
|
||||
|
@ -285,11 +284,6 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
|
|||
#define sci_init_pins_irda NULL
|
||||
#endif
|
||||
|
||||
#ifdef SCI_ONLY
|
||||
#define sci_init_pins_scif NULL
|
||||
#endif
|
||||
|
||||
#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
|
||||
static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
|
||||
{
|
||||
|
@ -449,7 +443,6 @@ static inline int scif_rxroom(struct uart_port *port)
|
|||
return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
|
||||
}
|
||||
#endif
|
||||
#endif /* SCIF_ONLY || SCI_AND_SCIF */
|
||||
|
||||
static inline int sci_txroom(struct uart_port *port)
|
||||
{
|
||||
|
@ -485,11 +478,9 @@ static void sci_transmit_chars(struct uart_port *port)
|
|||
return;
|
||||
}
|
||||
|
||||
#ifndef SCI_ONLY
|
||||
if (port->type == PORT_SCIF)
|
||||
count = scif_txroom(port);
|
||||
else
|
||||
#endif
|
||||
count = sci_txroom(port);
|
||||
|
||||
do {
|
||||
|
@ -519,12 +510,10 @@ static void sci_transmit_chars(struct uart_port *port)
|
|||
} else {
|
||||
ctrl = sci_in(port, SCSCR);
|
||||
|
||||
#if !defined(SCI_ONLY)
|
||||
if (port->type == PORT_SCIF) {
|
||||
sci_in(port, SCxSR); /* Dummy read */
|
||||
sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
|
||||
}
|
||||
#endif
|
||||
|
||||
ctrl |= SCI_CTRL_FLAGS_TIE;
|
||||
sci_out(port, SCSCR, ctrl);
|
||||
|
@ -547,11 +536,9 @@ static inline void sci_receive_chars(struct uart_port *port)
|
|||
return;
|
||||
|
||||
while (1) {
|
||||
#if !defined(SCI_ONLY)
|
||||
if (port->type == PORT_SCIF)
|
||||
count = scif_rxroom(port);
|
||||
else
|
||||
#endif
|
||||
count = sci_rxroom(port);
|
||||
|
||||
/* Don't copy more bytes than there is room for in the buffer */
|
||||
|
@ -810,26 +797,27 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr)
|
|||
|
||||
static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
|
||||
{
|
||||
unsigned short ssr_status, scr_status;
|
||||
struct uart_port *port = ptr;
|
||||
unsigned short ssr_status, scr_status;
|
||||
struct uart_port *port = ptr;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
ssr_status = sci_in(port,SCxSR);
|
||||
scr_status = sci_in(port,SCSCR);
|
||||
|
||||
/* Tx Interrupt */
|
||||
if ((ssr_status & 0x0020) && (scr_status & 0x0080))
|
||||
sci_tx_interrupt(irq, ptr);
|
||||
if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
|
||||
ret = sci_tx_interrupt(irq, ptr);
|
||||
/* Rx Interrupt */
|
||||
if ((ssr_status & 0x0002) && (scr_status & 0x0040))
|
||||
sci_rx_interrupt(irq, ptr);
|
||||
if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
|
||||
ret = sci_rx_interrupt(irq, ptr);
|
||||
/* Error Interrupt */
|
||||
if ((ssr_status & 0x0080) && (scr_status & 0x0400))
|
||||
sci_er_interrupt(irq, ptr);
|
||||
if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
|
||||
ret = sci_er_interrupt(irq, ptr);
|
||||
/* Break Interrupt */
|
||||
if ((ssr_status & 0x0010) && (scr_status & 0x0200))
|
||||
sci_br_interrupt(irq, ptr);
|
||||
if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
|
||||
ret = sci_br_interrupt(irq, ptr);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK)
|
||||
|
@ -1054,10 +1042,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
|
||||
sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
|
||||
|
||||
#if !defined(SCI_ONLY)
|
||||
if (port->type == PORT_SCIF)
|
||||
sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
|
||||
#endif
|
||||
|
||||
smr_val = sci_in(port, SCSMR) & 3;
|
||||
if ((termios->c_cflag & CSIZE) == CS7)
|
||||
|
|
|
@ -16,7 +16,6 @@
|
|||
# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
|
||||
# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
|
||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define SCI_AND_SCIF
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
# define SCIF0 0xA4400000
|
||||
# define SCIF2 0xA4410000
|
||||
|
@ -30,17 +29,15 @@
|
|||
* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
|
||||
*/
|
||||
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define SCIF_ONLY
|
||||
#define SCIF_ORER 0x0200 /* overrun error bit */
|
||||
#elif defined(CONFIG_SH_RTS7751R2D)
|
||||
# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
|
||||
# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
|
||||
|
@ -53,28 +50,24 @@
|
|||
# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
|
||||
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
|
||||
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
|
||||
# define SCI_AND_SCIF
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||
# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
|
||||
# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define PACR 0xa4050100
|
||||
# define PBCR 0xa4050102
|
||||
# define SCSCR_INIT(port) 0x3B
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
|
||||
# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
|
||||
# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
|
||||
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
|
||||
# define PADR 0xA4050120
|
||||
# define PSDR 0xA405013e
|
||||
|
@ -82,7 +75,6 @@
|
|||
# define PSCR 0xA405011E
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
|
||||
# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
|
||||
# define SCSPTR0 SCPDR0
|
||||
|
@ -97,12 +89,10 @@
|
|||
# define SCSPTR5 0xa4050128
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
||||
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
|
||||
# define SCIF_BASE_ADDR 0x01030000
|
||||
# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
|
||||
|
@ -111,14 +101,11 @@
|
|||
# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
|
||||
# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define SCI_ONLY
|
||||
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
|
||||
#elif defined(CONFIG_H8S2678)
|
||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define SCI_ONLY
|
||||
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
||||
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
||||
|
@ -126,20 +113,17 @@
|
|||
# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
|
||||
# define SCSPTR0 0xff923020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xff924020 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xff925020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
|
||||
|
@ -149,7 +133,6 @@
|
|||
# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
|
||||
# define SCIF_OPER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7206) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7263)
|
||||
|
@ -158,14 +141,12 @@
|
|||
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
|
||||
# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
|
||||
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
|
||||
|
@ -173,7 +154,6 @@
|
|||
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#else
|
||||
# error CPU subtype not defined
|
||||
#endif
|
||||
|
@ -186,6 +166,7 @@
|
|||
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7091) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7722) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
|
||||
|
@ -244,55 +225,28 @@
|
|||
# define SCIF_TXROOM_MAX 16
|
||||
#endif
|
||||
|
||||
#if defined(SCI_ONLY)
|
||||
# define SCxSR_TEND(port) SCI_TEND
|
||||
# define SCxSR_ERRORS(port) SCI_ERRORS
|
||||
# define SCxSR_RDxF(port) SCI_RDRF
|
||||
# define SCxSR_TDxE(port) SCI_TDRE
|
||||
# define SCxSR_ORER(port) SCI_ORER
|
||||
# define SCxSR_FER(port) SCI_FER
|
||||
# define SCxSR_PER(port) SCI_PER
|
||||
# define SCxSR_BRK(port) 0x00
|
||||
# define SCxSR_RDxF_CLEAR(port) 0xbc
|
||||
# define SCxSR_ERROR_CLEAR(port) 0xc4
|
||||
# define SCxSR_TDxE_CLEAR(port) 0x78
|
||||
# define SCxSR_BREAK_CLEAR(port) 0xc4
|
||||
#elif defined(SCIF_ONLY)
|
||||
# define SCxSR_TEND(port) SCIF_TEND
|
||||
# define SCxSR_ERRORS(port) SCIF_ERRORS
|
||||
# define SCxSR_RDxF(port) SCIF_RDF
|
||||
# define SCxSR_TDxE(port) SCIF_TDFE
|
||||
#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
|
||||
#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
|
||||
#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
|
||||
#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
|
||||
#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
|
||||
#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
|
||||
#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
# define SCxSR_ORER(port) SCIF_ORER
|
||||
# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
|
||||
#else
|
||||
# define SCxSR_ORER(port) 0x0000
|
||||
# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
|
||||
#endif
|
||||
# define SCxSR_FER(port) SCIF_FER
|
||||
# define SCxSR_PER(port) SCIF_PER
|
||||
# define SCxSR_BRK(port) SCIF_BRK
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||
# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
|
||||
# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
|
||||
# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
|
||||
# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
|
||||
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
|
||||
# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
|
||||
# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
|
||||
# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
|
||||
#else
|
||||
/* SH7705 can also use this, clearing is same between 7705 and 7709 */
|
||||
# define SCxSR_RDxF_CLEAR(port) 0x00fc
|
||||
# define SCxSR_ERROR_CLEAR(port) 0x0073
|
||||
# define SCxSR_TDxE_CLEAR(port) 0x00df
|
||||
# define SCxSR_BREAK_CLEAR(port) 0x00e3
|
||||
#endif
|
||||
#else
|
||||
# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
|
||||
# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
|
||||
# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
|
||||
# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
|
||||
# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
|
||||
# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
|
||||
# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
|
||||
# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
|
||||
# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
|
||||
# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
|
||||
# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
|
||||
|
@ -574,18 +528,20 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7091) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7091)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
#ifndef SCIF_ONLY
|
||||
if (port->mapbase == 0xffe00000)
|
||||
return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
|
||||
#endif
|
||||
#ifndef SCI_ONLY
|
||||
if (port->mapbase == 0xffe80000)
|
||||
return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffe80000)
|
||||
return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||
|
@ -651,7 +607,7 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
|
||||
return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
|
||||
}
|
||||
#elif defined(__H8300H__) || defined(__H8300S__)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
|
|
Loading…
Reference in a new issue