omap3: rx51: Add SDRAM init
This patch adds board specific SDRAM init for RX51. This patch is a collaboration of work from following people: Juha Yrjola: Original code Lauri Leukkunen: Port to RX51 Tero Kristo: Support for multiple OPP:s, merge of patches Samu Onkalo: Fixed SDRAM parameters according to specs Kalle Jokiniemi: A fix for rounding error Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Cc: Samu Onkalo <samu.p.onkalo@nokia.com> Cc: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Cc: Lauri Leukkunen <lauri.leukkunen@nokia.com> Cc: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>hifive-unleashed-5.1
Tero Kristo
Tony Lindgren
parent
58c54e156c
commit
2000655ee7
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@ -72,6 +72,7 @@ obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \
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mmc-twl4030.o
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obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
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obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
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board-rx51-sdram.o \
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board-rx51-peripherals.o \
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mmc-twl4030.o
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obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \
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@ -0,0 +1,221 @@
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/*
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* SDRC register values for RX51
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*
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* Copyright (C) 2008 Nokia Corporation
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*
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* Lauri Leukkunen <lauri.leukkunen@nokia.com>
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*
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* Original code by Juha Yrjola <juha.yrjola@solidboot.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <plat/io.h>
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#include <plat/common.h>
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#include <plat/clock.h>
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#include <plat/sdrc.h>
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/* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
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struct sdram_timings {
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u32 casl;
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u32 tDAL;
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u32 tDPL;
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u32 tRRD;
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u32 tRCD;
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u32 tRP;
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u32 tRAS;
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u32 tRC;
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u32 tRFC;
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u32 tXSR;
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u32 tREF; /* in ns */
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u32 tXP;
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u32 tCKE;
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u32 tWTR;
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};
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struct omap_sdrc_params rx51_sdrc_params[4];
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static const struct sdram_timings rx51_timings[] = {
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{
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.casl = 3,
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.tDAL = 33000,
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.tDPL = 15000,
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.tRRD = 12000,
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.tRCD = 22500,
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.tRP = 18000,
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.tRAS = 42000,
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.tRC = 66000,
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.tRFC = 138000,
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.tXSR = 200000,
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.tREF = 7800,
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.tXP = 2,
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.tCKE = 2,
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.tWTR = 2
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},
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};
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static unsigned long sdrc_get_fclk_period(long rate)
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{
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/* In picoseconds */
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return 1000000000 / rate;
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}
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static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate)
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{
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unsigned long tick_ps;
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/* Calculate in picosecs to yield more exact results */
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tick_ps = sdrc_get_fclk_period(rate);
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return (time_ps + tick_ps - 1) / tick_ps;
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}
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#undef DEBUG
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#ifdef DEBUG
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static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
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int ticks, long rate, const char *name)
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#else
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static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
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int ticks)
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#endif
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{
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int mask, nr_bits;
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nr_bits = end_bit - st_bit + 1;
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if (ticks >= 1 << nr_bits)
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return -1;
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mask = (1 << nr_bits) - 1;
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*regval &= ~(mask << st_bit);
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*regval |= ticks << st_bit;
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#ifdef DEBUG
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printk(KERN_INFO "SDRC %s: %i ticks %i ns\n", name, ticks,
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(unsigned int)sdrc_get_fclk_period(rate) * ticks /
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1000);
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#endif
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return 0;
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}
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#ifdef DEBUG
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#define SDRC_SET_ONE(reg, st, end, field, rate) \
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if (set_sdrc_timing_regval((reg), (st), (end), \
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rx51_timings->field, (rate), #field) < 0) \
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err = -1;
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#else
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#define SDRC_SET_ONE(reg, st, end, field, rate) \
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if (set_sdrc_timing_regval((reg), (st), (end), \
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rx51_timings->field) < 0) \
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err = -1;
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#endif
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#ifdef DEBUG
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static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
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int time, long rate, const char *name)
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#else
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static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
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int time, long rate)
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#endif
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{
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int ticks, ret;
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ret = 0;
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if (time == 0)
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ticks = 0;
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else
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ticks = sdrc_ps_to_ticks(time, rate);
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#ifdef DEBUG
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ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks,
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rate, name);
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#else
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ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks);
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#endif
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return ret;
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}
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#ifdef DEBUG
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#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
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if (set_sdrc_timing_regval_ps((reg), (st), (end), \
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rx51_timings->field, \
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(rate), #field) < 0) \
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err = -1;
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#else
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#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
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if (set_sdrc_timing_regval_ps((reg), (st), (end), \
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rx51_timings->field, (rate)) < 0) \
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err = -1;
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#endif
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static int sdrc_timings(int id, long rate)
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{
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u32 ticks_per_ms;
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u32 rfr, l;
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u32 actim_ctrla = 0, actim_ctrlb = 0;
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u32 rfr_ctrl;
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int err = 0;
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long l3_rate = rate / 1000;
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SDRC_SET_ONE_PS(&actim_ctrla, 0, 4, tDAL, l3_rate);
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SDRC_SET_ONE_PS(&actim_ctrla, 6, 8, tDPL, l3_rate);
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SDRC_SET_ONE_PS(&actim_ctrla, 9, 11, tRRD, l3_rate);
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SDRC_SET_ONE_PS(&actim_ctrla, 12, 14, tRCD, l3_rate);
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SDRC_SET_ONE_PS(&actim_ctrla, 15, 17, tRP, l3_rate);
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SDRC_SET_ONE_PS(&actim_ctrla, 18, 21, tRAS, l3_rate);
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SDRC_SET_ONE_PS(&actim_ctrla, 22, 26, tRC, l3_rate);
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SDRC_SET_ONE_PS(&actim_ctrla, 27, 31, tRFC, l3_rate);
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SDRC_SET_ONE_PS(&actim_ctrlb, 0, 7, tXSR, l3_rate);
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SDRC_SET_ONE(&actim_ctrlb, 8, 10, tXP, l3_rate);
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SDRC_SET_ONE(&actim_ctrlb, 12, 14, tCKE, l3_rate);
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SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate);
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ticks_per_ms = l3_rate;
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rfr = rx51_timings[0].tREF * ticks_per_ms / 1000000;
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if (rfr > 65535 + 50)
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rfr = 65535;
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else
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rfr -= 50;
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#ifdef DEBUG
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printk(KERN_INFO "SDRC tREF: %i ticks\n", rfr);
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#endif
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l = rfr << 8;
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rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */
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rx51_sdrc_params[id].rate = rate;
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rx51_sdrc_params[id].actim_ctrla = actim_ctrla;
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rx51_sdrc_params[id].actim_ctrlb = actim_ctrlb;
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rx51_sdrc_params[id].rfr_ctrl = rfr_ctrl;
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rx51_sdrc_params[id].mr = 0x32;
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rx51_sdrc_params[id + 1].rate = 0;
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return err;
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}
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struct omap_sdrc_params *rx51_get_sdram_timings(void)
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{
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int err;
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err = sdrc_timings(0, 41500000);
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err |= sdrc_timings(1, 83000000);
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err |= sdrc_timings(2, 166000000);
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return &rx51_sdrc_params[0];
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}
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@ -30,6 +30,8 @@
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#include <plat/gpmc.h>
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#include <plat/usb.h>
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struct omap_sdrc_params *rx51_get_sdram_timings(void);
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static struct omap_lcd_config rx51_lcd_config = {
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.ctrl_name = "internal",
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};
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@ -55,9 +57,12 @@ static struct omap_board_config_kernel rx51_config[] = {
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static void __init rx51_init_irq(void)
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{
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struct omap_sdrc_params *sdrc_params;
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omap_board_config = rx51_config;
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omap_board_config_size = ARRAY_SIZE(rx51_config);
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omap2_init_common_hw(NULL, NULL);
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sdrc_params = rx51_get_sdram_timings();
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omap2_init_common_hw(sdrc_params, sdrc_params);
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omap_init_irq();
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omap_gpio_init();
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}
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