spi/bfin_spi: drop custom cs_change_per_word support
As David points out, the cs_change_per_word option isn't standard, nor is anyone actually using it. So punt all of the dead code considering it makes up ~10% of the code size. Reported-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -120,7 +120,6 @@ struct bfin5xx_spi_chip {
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u16 ctl_reg;
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u8 enable_dma;
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u8 bits_per_word;
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u8 cs_change_per_word;
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u16 cs_chg_udelay; /* Some devices require 16-bit delays */
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u32 cs_gpio;
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/* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
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@ -114,7 +114,6 @@ struct chip_data {
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u8 width; /* 0 or 1 */
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u8 enable_dma;
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u8 bits_per_word; /* 8 or 16 */
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u8 cs_change_per_word;
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u16 cs_chg_udelay; /* Some devices require > 255usec delay */
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u32 cs_gpio;
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u16 idle_tx_val;
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@ -309,24 +308,6 @@ static void bfin_spi_u8_writer(struct driver_data *drv_data)
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}
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}
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static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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/* clear RXS (we check for RXS inside the loop) */
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bfin_spi_dummy_read(drv_data);
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while (drv_data->tx < drv_data->tx_end) {
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bfin_spi_cs_active(drv_data, chip);
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
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/* make sure transfer finished before deactiving CS */
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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cpu_relax();
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bfin_spi_dummy_read(drv_data);
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bfin_spi_cs_deactive(drv_data, chip);
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}
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}
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static void bfin_spi_u8_reader(struct driver_data *drv_data)
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{
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u16 tx_val = drv_data->cur_chip->idle_tx_val;
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@ -342,24 +323,6 @@ static void bfin_spi_u8_reader(struct driver_data *drv_data)
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}
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}
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static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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u16 tx_val = chip->idle_tx_val;
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/* discard old RX data and clear RXS */
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bfin_spi_dummy_read(drv_data);
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while (drv_data->rx < drv_data->rx_end) {
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bfin_spi_cs_active(drv_data, chip);
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write_TDBR(drv_data, tx_val);
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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cpu_relax();
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*(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
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bfin_spi_cs_deactive(drv_data, chip);
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}
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}
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static void bfin_spi_u8_duplex(struct driver_data *drv_data)
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{
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/* discard old RX data and clear RXS */
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@ -373,23 +336,6 @@ static void bfin_spi_u8_duplex(struct driver_data *drv_data)
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}
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}
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static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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/* discard old RX data and clear RXS */
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bfin_spi_dummy_read(drv_data);
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while (drv_data->rx < drv_data->rx_end) {
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bfin_spi_cs_active(drv_data, chip);
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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cpu_relax();
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*(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
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bfin_spi_cs_deactive(drv_data, chip);
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}
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}
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static void bfin_spi_u16_writer(struct driver_data *drv_data)
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{
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/* clear RXS (we check for RXS inside the loop) */
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@ -407,25 +353,6 @@ static void bfin_spi_u16_writer(struct driver_data *drv_data)
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}
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}
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static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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/* clear RXS (we check for RXS inside the loop) */
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bfin_spi_dummy_read(drv_data);
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while (drv_data->tx < drv_data->tx_end) {
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bfin_spi_cs_active(drv_data, chip);
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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drv_data->tx += 2;
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/* make sure transfer finished before deactiving CS */
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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cpu_relax();
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bfin_spi_dummy_read(drv_data);
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bfin_spi_cs_deactive(drv_data, chip);
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}
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}
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static void bfin_spi_u16_reader(struct driver_data *drv_data)
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{
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u16 tx_val = drv_data->cur_chip->idle_tx_val;
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@ -442,25 +369,6 @@ static void bfin_spi_u16_reader(struct driver_data *drv_data)
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}
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}
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static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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u16 tx_val = chip->idle_tx_val;
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/* discard old RX data and clear RXS */
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bfin_spi_dummy_read(drv_data);
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while (drv_data->rx < drv_data->rx_end) {
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bfin_spi_cs_active(drv_data, chip);
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write_TDBR(drv_data, tx_val);
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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cpu_relax();
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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drv_data->rx += 2;
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bfin_spi_cs_deactive(drv_data, chip);
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}
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}
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static void bfin_spi_u16_duplex(struct driver_data *drv_data)
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{
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/* discard old RX data and clear RXS */
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@ -476,25 +384,6 @@ static void bfin_spi_u16_duplex(struct driver_data *drv_data)
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}
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}
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static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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/* discard old RX data and clear RXS */
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bfin_spi_dummy_read(drv_data);
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while (drv_data->rx < drv_data->rx_end) {
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bfin_spi_cs_active(drv_data, chip);
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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drv_data->tx += 2;
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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cpu_relax();
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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drv_data->rx += 2;
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bfin_spi_cs_deactive(drv_data, chip);
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}
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}
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/* test if ther is more transfer to be done */
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static void *bfin_spi_next_transfer(struct driver_data *drv_data)
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{
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@ -773,23 +662,17 @@ static void bfin_spi_pump_transfers(unsigned long data)
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case 8:
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drv_data->n_bytes = 1;
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width = CFG_SPI_WORDSIZE8;
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drv_data->read = chip->cs_change_per_word ?
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bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
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drv_data->write = chip->cs_change_per_word ?
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bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
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drv_data->duplex = chip->cs_change_per_word ?
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bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
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drv_data->read = bfin_spi_u8_reader;
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drv_data->write = bfin_spi_u8_writer;
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drv_data->duplex = bfin_spi_u8_duplex;
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break;
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case 16:
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drv_data->n_bytes = 2;
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width = CFG_SPI_WORDSIZE16;
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drv_data->read = chip->cs_change_per_word ?
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bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
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drv_data->write = chip->cs_change_per_word ?
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bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
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drv_data->duplex = chip->cs_change_per_word ?
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bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
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drv_data->read = bfin_spi_u16_reader;
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drv_data->write = bfin_spi_u16_writer;
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drv_data->duplex = bfin_spi_u16_duplex;
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break;
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default:
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@ -1164,7 +1047,6 @@ static int bfin_spi_setup(struct spi_device *spi)
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&& drv_data->master_info->enable_dma;
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chip->ctl_reg = chip_info->ctl_reg;
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chip->bits_per_word = chip_info->bits_per_word;
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chip->cs_change_per_word = chip_info->cs_change_per_word;
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chip->cs_chg_udelay = chip_info->cs_chg_udelay;
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chip->cs_gpio = chip_info->cs_gpio;
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chip->idle_tx_val = chip_info->idle_tx_val;
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@ -1193,23 +1075,17 @@ static int bfin_spi_setup(struct spi_device *spi)
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case 8:
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chip->n_bytes = 1;
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chip->width = CFG_SPI_WORDSIZE8;
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chip->read = chip->cs_change_per_word ?
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bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
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chip->write = chip->cs_change_per_word ?
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bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
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chip->duplex = chip->cs_change_per_word ?
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bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
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chip->read = bfin_spi_u8_reader;
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chip->write = bfin_spi_u8_writer;
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chip->duplex = bfin_spi_u8_duplex;
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break;
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case 16:
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chip->n_bytes = 2;
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chip->width = CFG_SPI_WORDSIZE16;
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chip->read = chip->cs_change_per_word ?
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bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
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chip->write = chip->cs_change_per_word ?
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bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
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chip->duplex = chip->cs_change_per_word ?
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bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
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chip->read = bfin_spi_u16_reader;
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chip->write = bfin_spi_u16_writer;
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chip->duplex = bfin_spi_u16_duplex;
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break;
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default:
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